Chip giant NVIDIA kicked off its annual Graphics Processing Unit (GPU) Technology Conference (GTC) today, with CEO Jensen Huang announcing the launch of the new artificial intelligence chip, Blackwell B200.

According to a report from TechNews, this new architecture, Blackwell, boasts a massive GPU volume, crafted using TSMC’s 4-nanometer (4NP) process technology, integrating two independently manufactured dies, totaling 208 billion transistors. These dies are then bound together like a zipper through the NVLink 5.0 interface.

NVIDIA utilizes a 10 TB/sec NVLink 5.0 to connect the two dies, officially termed NV-HBI interface. The NVLink 5.0 interface of the Blackwell complex provides 1.8 TB/sec bandwidth, doubling the speed of the NVLink 4.0 interface on the previous generation Hopper architecture GPU.

As per a report from Tom’s Hardware, the AI computing performance of a single B200 GPU can reach 20 petaflops, whereas the previous generation H100 offered a maximum of only 4 petaflops of AI computing performance. The B200 will also be paired with 192GB of HBM3e memory, providing up to 8 TB/s of bandwidth.

NVIDIA’s HBM supplier, South Korean chipmaker SK Hynix, also issued a press release today announcing the commencement of mass production of its high-performance DRAM new product, HBM3e, with shipments set to begin at the end of March.

Source: SK Hynix

Recently, global tech companies have been heavily investing in AI, leading to increasing demands for AI chip performance. SK Hynix points out that HBM3e is the optimal product to meet these demands. As memory operations for AI are extremely fast, efficient heat dissipation is crucial. HBM3e incorporates the latest Advanced MR-MUF technology for heat dissipation control, resulting in a 10% improvement in cooling performance compared to the previous generation.

Per SK Hynix’s press release, Sungsoo Ryu, the head of HBM Business at SK Hynix, said that mass production of HBM3e has completed the company’s lineup of industry-leading AI memory products.

“With the success story of the HBM business and the strong partnership with customers that it has built for years, SK hynix will cement its position as the total AI memory provider,” he stated.

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• [News] Foxconn Capitalizes on AI Opportunities? Reportedly Looking at Apple’s AI Server Market, B200 Also Poised to Succeed
• [News] NVIDIA and AMD Clash in AI Chip Market, as TSMC Dominates Orders with Strong Momentum in Advanced Processes

(Photo credit: NVIDIA)

Benefited from robust demand in downstream application markets, the silicon carbide (SiC) industry is in high gear. According to TrendForce, the SiC power device market is expected to reach USD 5.33 billion by 2026, with its mainstream applications still highly reliant on electric vehicles and renewable energy sources.

Recently, the widely-publicized SiC market has seen new developments involving companies such as Mitsubishi Electric, Mersen, and Ascen Power.

• Mitsubishi Electric to Begin Construction of SiC Fab in April

According to recent reports from Nikkei, Mitsubishi Electric plans to commence construction of a new 8-inch SiC fab in Kumamoto Prefecture, Japan, in April 2024, with operations scheduled to start in April 2026.

In March 2023, Mitsubishi Electric announced the plan to invest approximately JPY 100 billion (Around CNY 4.856 billion) over five years to construct an 8-inch SiC fab and enhance related production facilities. The fab is projected to kick-start operation in April 2026.

The new fab, spanning six floors with a total floor area of around 42,000 square meters, will primarily handle front-end processes for 8-inch SiC wafers. Mitsubishi Electric will introduce an automated transport system across all processes to create a highly efficient production line and plans to gradually increase capacity, aiming to increase SiC production capacity by five times by the fiscal year 2026 (compared to fiscal year 2022).

In May 2023, Mitsubishi Electric signed a MOU with Coherent to supply 8-inch n-type 4HSiC wafers for the new factory. Both parties are committed to expanding the production scale of 8-inch SiC devices.

• Ascen Power Accelerates Phase One Capacity Ramp-up of SiC Chip Manufacturing Project

Recently, Shao Yonghua, the plant manager of Ascen Power’s fab, introduced that the entire fab is currently ramping up capacity, with the planned capacity of producing 240,000 pieces of 6-inch automotive-grade SiC chips annually expected to be achieved by the end of this year.

The reserved 8-inch production line is adjacent to the 6-inch line and will have the capability to produce 240,000 pieces of 8-inch automotive-grade SiC chips annually once completed.

As previously reported, Ascen Power’s SiC chip manufacturing project is a major project under Guangdong’s “Strengthening Chip Technology Project,” with a total investment of CNY 7.5 billion, covering an area of 150 acres.

The first phase involves an investment of CNY 3.5 billion to build a production line capable of producing 240,000 pieces of 6-inch SiC chips annually, with the second phase focusing on establishing a production line capable of producing 240,000 pieces of 8-inch SiC chips annually. The products include IGBTs, SiC SBD/JBS, SiC MOSFETs, targeting applications including new energy vehicles, photovoltaics, smart grids.

In November 2022, the project’s clean room was officially put into use, achieving a monthly production capacity of 10,000 pieces. Its automotive-grade and industrial-grade chips have been successfully mass-produced and sampled, and these chips are about to complete the automotive verification. Up to now, Ascen Power has signed agreements with more than 40 customers and achieved tape-out, covering most SiC chip design companies nationwide.

• Mersen To Rev up SiC Wafer Production

On March 12, European graphite materials and silicon carbide wafer supplier Mersen announced that it has received investment from the French government for capacity expansion of its SiC wafer project. The subsidy amount may exceed Euro 12 million (Approximately CNY 94 million), sourced from the “France 2023 Plan”—a significant joint interest project in microelectronics and communication technology in Europe.

Mersen stated that they intend to advance the research and industrial production of p-SiC wafers with this investment. p-SiC is a low-resistivity polycrystalline SiC wafer that can be combined with single-crystal SiC active layers, enabling SiC device manufacturers to improve production yield and transistor performance.

Mersen expects to invest Euro 85 million (Approximately CNY 670 million) between 2023 and 2025, employ 80 to 100 staff, promote capacity construction at the Gennevilliers plant in France, and accomplish a potential manufacturing capacity of 400,000 wafers (150mm) by 2027.

Additionally, Mersen will supply SiC wafers to Soitec. In November 2021, two sides entered into a strategic partnership to jointly develop polycrystalline SiC wafers with extremely low resistivity for SiC power electronic components based on Soitec SmartSiC technology, leveraging their respective expertise in substrates and materials.

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• [News] Continuous Breakthroughs in SiC Substrates, Global 8-Inch Fab to Reach 11

(Photo credit: Mitsubishi Electric)

According to sources cited by Reuters,  TSMC is reportedly considering plans to establish a production line for its CoWoS technology in Japan. However, TSMC has yet to make any further decisions, and they have declined to comment on the matter.

CoWoS is an advanced packaging technology that stacks chips to enhance computing power, reduce energy consumption, and save space. Currently, TSMC’s CoWoS production capacity is entirely located in Taiwan.

With the booming development of artificial intelligence, global demand for advanced semiconductor packaging has surged, prompting chip suppliers like TSMC, Samsung, and Intel to strengthen their advanced packaging capabilities.

Previously, TSMC’s CEO, C.C. Wei, stated that the company plans to double its CoWoS output by the end of 2024 and further increase it in 2025. With TSMC recently completing the first phase of construction for its Kumamoto fab in Japan and announcing plans for the second phase, which will involve collaboration with Japanese companies SONY Semiconductor Solutions and Toyota Motor Corporation, with a total investment exceeding USD 20 billion and utilizing 6/7-nanometer advanced processes.

However, Joanne Chiao, an analyst at market research firm TrendForce, suggests that if TSMC establishes advanced packaging capacity in Japan, it may face limitations in scale. It remains unclear how much demand there is in Japan for CoWoS packaging, but most of TSMC’s CoWoS customers are currently in the United States.

Additionally, sources cited by Reuters’ report indicate that TSMC’s competitor, Intel, is also considering establishing an advanced packaging research facility in Japan to deepen ties with local chip supply chain companies.

Meanwhile, Samsung, another competitor of TSMC, is setting up advanced packaging research facilities in Yokohama, Japan, with government support. Furthermore, Samsung is in discussions with Japanese and other companies regarding material procurement, preparing to launch its packaging technology similar to that used by SK Hynix.

Regarding the development of the semiconductor industry in Japan, as mentioned in a previous report from TrendForce, Japan’s resurgence in the semiconductor arena is palpable, with the Ministry of Economy, Trade, and Industry fostering multi-faceted collaborations with the private sector. With a favorable exchange rate policy aiding factory construction and investments, the future looks bright for exports.

However, the looming shortage of semiconductor talent in Japan is a concern. In response, there are generous subsidy programs for talent development. Japan is strategically positioning itself to reclaim its former glory in the world of semiconductors.

Read more

• [News] Subsidies to TSMC from Japan and China Increase Over Fivefold Annually
• [News] High Efficiency in TSMC Kumamoto Plant Construction Sets Stage for Potential Advanced Packaging Investment in Japan

(Photo credit: TSMC)

The Executive Yuan and TSMC have reportedly reached a consensus on the investment project for the new advanced packaging plant at the TSMC Science Park in Chiayi. According to a report from Economic Daily News, six new plant sites will be allocated to TSMC in the Science Park, two more than originally anticipated, with a total investment exceeding NTD 500 billion. The expansion is expected to increase CoWoS advanced packaging capacity and to be announced to the public in early April.

TSMC has refrained from commenting on the matter. Regarding the news, the Executive Yuan actively coordinated with TSMC for the establishment of the advanced packaging plant in the Chiayi Science Park located in Taibao. The related environmental assessments and water and electricity facilities have been processed, with construction expected to commence in April, indirectly confirming the rumors.

As per sources cited by the report, Chiayi Science Park is poised to become a new hub for TSMC’s advanced packaging capacity. Among the six new scheduled plants, construction will begin on two this year, aligning with the Executive Yuan’s statement of construction commencement in April.

TSMC’s extensive expansion is primarily driven by the high demand for advanced packaging. For instance,  in the case of the NVIDIA H100, after integrating components via CoWoS, each wafer yields approximately 28 chips. However, for the upcoming B100, with increased volume and integration, the yield per wafer drops to just 16 chips.

On the other hand, TSMC’s advanced processes, per a previous report from Commercial Times, remained fully utilized, with capacity utilization exceeding 90% in February, driven by sustained AI demand. The same report also noted that NVIDIA’s orders to TSMC are robust, pushing TSMC’s 3 and 4-nanometer production capacity to nearly full utilization.

As each new generation of NVIDIA’s AI chips integrates CoWoS, chip output is halved, yet demand for AI servers continues to soar. With terminal demand skyrocketing while chip output dwindles, there’s a “cliff-like gap” in CoWoS advanced packaging capacity. TSMC must ramp up CoWoS production swiftly to ensure uninterrupted customer supply.

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• [News] SK Hynix Reportedly Invests USD 1 Billion in Advanced Packaging to Strengthen HBM Chip Leadership
• [News] TSMC Reportedly Doubles CoWoS Capacity while Amkor, ASE also Enter Advanced Packaging for AI

(Photo credit: TSMC)

“It is not the shortage of AI chips, it is the shortage of our CoWoS capacity,” replied TSMC Chairman Mark Liu during an interview in September last year, propelling this technology that TSMC had quietly cultivated for over a decade into a global spotlight.

As per a report from TechNews, the hardware demand sparked by generative AI has also led to “advanced packaging” becoming not only a hot keyword pursued by global investors but also a prominent feature of the semiconductor industry. From foundries and memory manufacturers to OASTs, all are actively involved in the research and capacity expansion of advanced packaging technologies.

TSMC, the leading force in the advanced packaging market, has repeatedly emphasized its efforts to expand capacity during its earnings call, including capacity expansions in Zhunan and Hsinchu, and even the possibility of constructing advanced packaging facilities in Chiayi.

Intel’s strategic moves also underscore its emphasis on the development of advanced packaging. Intel’s new plant completed in Penang, Malaysia in 2023 is aimed at establishing advanced packaging capacity.

Leading packaging and testing company, ASE Technology Holding, has also actively participated in the competition for advanced packaging. Apart from its subsidiary, Siliconware Precision Industries (SPIL), which is already a supplier for the backend packaging of CoWoS, ASE Technology Holding is also expanding advanced packaging capacity at its facility in Kaohsiung.

Memory manufacturers are also aggressively ramping up their advanced packaging capacity. SK Hynix, which exclusively supplies HBM for NVIDIA AI chips, recently announced plans to invest USD 1 billion in the development of advanced packaging. They view advanced packaging as the “future focus of semiconductor development for the next 50 years.

Advanced Packaging: Over a Decade of Development

In fact, advanced packaging is not a new concept. Tracing the history of packaging technology, the year 2000 undoubtedly marked a turning point. From this year onwards, packaging technology shifted from traditional wire bonding and flip-chip methods to “wafer-level packaging,” where most or all packaging and testing processes are conducted on the wafer itself.

The 2.5D packaging, which gained significant attention after 2023, actually emerged as early as 2010. However, due to cost concerns, the number of manufacturers adopting this technology was relatively limited, with a focus on high-performance computing chips.

Chiang Shang-yi, the Chief Strategy Officer of Foxconn Semiconductor, recalled the initial lack of interest in CoWoS technology, which even led to him being regarded as a “joke” within the company( TSMC) for proposing advanced packaging. He also revealed that the first company willing to adopt the costly CoWoS technology was actually Huawei.

▲ Semiconductor Packaging Technology Evolution compiled by McKinsey, Accelerated Technological Evolution after 2000 (Source: McKinsey)

Compared to 2D packaging technology, 2.5D packaging involves placing an intermediate layer between the chip and the IC substrate and stacking different chips in parallel. TSMC’s CoWoS has become synonymous with 2.5D packaging, where a silicon interposer layer is inserted between the chip and the SiP substrate, and metal layers are connected using Through-Silicon Vias (TSVs) to overcome the density limitations of SiP substrates, which previously restricted the number of chips.

Despite TSMC’s dominance, Intel, with its extensive technical expertise in CPU packaging, cannot be underestimated. In the 2.5D packaging battlefield, Intel employs EMIB technology as its strategy. Unlike CoWoS, EMIB does not utilize a silicon interposer layer.

Instead, its key feature lies in the “Silicon Bridge,” buried within the packaging substrate, which connects the bare dies. Intel believes that EMIB offers cost advantages compared to solutions using large silicon interposer layers.

In recent years, Samsung, which has been actively cultivating the semiconductor foundry market, has also ventured into the 2.5D packaging arena. Their proprietary I-Cube technology has traditionally targeted applications in High-Performance Computing (HPC) chips. When Samsung introduced I-Cube4 in 2021, it emphasized the integration of multiple logic dies and HBM placed on a silicon interposer layer, enabling heterogeneous integration into a single chip.

As Moore’s Law approaches its limits and the massive computational demands triggered by generative AI continue to surge, coupled with the trend towards lighter, thinner, and smaller end products, chips are inevitably evolving towards more transistors, greater computational power, and lower power consumption performance.

Therefore, the transition of packaging technology from 2.5D to 3D is undoubtedly an inevitable development.

The difference between 3D and 2.5D packaging lies in the stacking method. In 2.5D packaging, chips are stacked parallelly on an intermediate layer, while in 3D packaging, chips are stacked vertically in a three-dimensional manner.

The advantage of 3D packaging lies in its ability to create more space for transistors within a chip through stacking, shorten the distance between different bare dies significantly, enhance transmission efficiency, and reduce power consumption during transmission.

TSMC, Intel, and Samsung Racing for 3D Packaging Technology

TSMC’s positioning in 3D IC technology is undeniable. Its SoIC technology adopts the wafer-to-wafer bonding technique. SoIC integrates homogeneous and heterogeneous small dies into a single chip, with smaller dimensions and a thinner profile. It can be integrated into 2.5D CoWoS or InFO. From an external perspective, SoIC resembles a universal SoC chip but integrates various functions heterogeneously.

Intel’s layout in 3D packaging revolves around its 3D Foveros technology. Structurally, the bottom layer comprises a packaging substrate, with a bottom wafer placed on top serving as an intermediate layer. Within this intermediate layer, numerous TSVs (Through-Silicon Vias) are present, facilitating connections between the upper chips, modules, and other parts of the system to achieve transmission purposes.

Samsung’s X-Cube 3D packaging technology utilizes TSV processes. Currently, Samsung’s X-Cube test chips can stack the SRAM layer on top of the logic layer, interconnected via TSVs, employing its 7nm EUV process technology.

TSMC’s Comprehensive Ecosystem Strategy

Currently dominating the advanced packaging market, thanks to its acquisition of large contracts for manufacturing NVIDIA AI chips, TSMC is not only continuing to develop more advanced packaging technologies but is also actively promoting its 3D Fabric platform.

In addition to incorporating the three key packaging technologies CoWoS, InFo, and SoIC, this platform has expanded into an industry alliance. It includes participation from EDA, IP, DCA/VCA, memory, packaging and testing suppliers, as well as substrate and testing vendors. The goal is to create a complete 3D Fabric ecosystem, strengthen innovation, and enhance customer adoption willingness.

This alliance has attracted active participation from heavyweight players in the semiconductor upstream supply chain. Even companies traditionally seen as competitors in the packaging and testing sector, such as Amkor, ASE Technology Holding, and Siliconware Precision Industries (SPIL), are members. The comprehensive supply chain has become a significant advantage for TSMC in providing advanced packaging contract manufacturing services.

▲ TSMC’s 3D Fabric Alliance members, including major players from EDA to packaging and testing companies. (Image Source: TSMC)

In comparison, Intel, despite its robust technological expertise developed over many years and its proposition to independently provide wafer manufacturing or testing services, faces a disadvantage in expanding its market share in advanced packaging due to its lack of experience in the foundry market.

On the other hand, Samsung, compared to TSMC, is constrained by its yield issues in advanced processes. This limitation leads IC design companies to prioritize foundries with more stable yields when considering outsourcing comprehensive manufacturing services.

Read more

• [News] SK Hynix Reportedly Invests USD 1 Billion in Advanced Packaging to Strengthen HBM Chip Leadership
• [News] TSMC Reportedly Doubles CoWoS Capacity while Amkor, ASE also Enter Advanced Packaging for AI

(Photo credit: TSMC)