In June 2023, leading processor manufacturer Intel reached an agreement with the German federal government, announcing the signing of an amended investment memorandum. The plan involves investing over EUR 30 billion to construct two new fabs in Magdeburg. The German federal government has agreed to provide a subsidy of EUR 10 billion, including incentives and subsidies from the European Chips Act and government initiatives.

According to a report by Tom’s Hardware citing sources, Intel has submitted conceptual drawings for a new fab in Germany. The initial plans include two fabs, designated as Fab 29.1 and Fab 29.2, equipped with the world’s most advanced semiconductor tools.

Moreover, Intel reportedly has ample space for up to six additional fabs. The first batch of two fabs is expected to commence operations in the fourth quarter of 2027, with both the Intel 14A (1.4nm) and Intel 10A (1nm) advanced processes believed to be part of the plan.

As per previous reports from TechNews, Intel has not disclosed any details regarding the 10A node, but it promises at least double-digit improvements in power consumption and performance. Intel CEO Pat Gelsinger has previously stated that new processes typically improve critical dimensions by approximately 14% to 15%. Therefore, it is plausible that the 10A and 14A nodes will also experience similar improvements.

Source: Intel

As per Intel’s roadmap, Intel 14A is also optimized in 2027, so it seems that 10A falls between 14A and 14A-E.

The report from Tom’s Hardware further indicates that Fab 29.1 and Fab 29.2, the two three-story buildings, occupy approximately 81,000 square meters, with a total length of 530 meters and a width of 153 meters. Each floor has a height ranging from 5.7 to 6.5 meters. Including the roof structure for air conditioning and heating, the building reaches a height of 36.7 meters.

The High-NA EUV exposure machines are installed on the second floor with a height of 6.5 meters, while the upper and lower floors are used for material logistics, providing necessary resources such as water, electricity, and chemicals.

ASML models that the 1st generation of the High-NA-enabled production node will employ between 4 to 9 High-NA EUV exposures and a total of 20 to 30 EUV exposures, encompassing both Low-NA and High-NA.

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• [News] Advancing into Intel 10A! Intel’s 2027 Blueprint Adds 1-Nanometer Process
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(Photo credit: Intel)

NVIDIA has yet to officially announce the exact release dates for its next-generation AI chip architectures, the Blackwell GPU, and the B100 chip. However, Dell’s Chief Operating Officer, Jeff Clarke, recently revealed ahead of schedule during Dell’s Q4 2024 Earnings Call that NVIDIA is set to introduce the Blackwell architecture next year, with plans to release not only the B100 chip but also another variant, the B200 chip.

Following Dell’s recent financial report, Clarke disclosed in a press release that NVIDIA is set to unveil the B200 product featuring the Blackwell architecture in 2025.

Clarke also mentioned that Dell’s flagship product, the PowerEdge XE9680 rack server, utilizes NVIDIA GPUs, making it the fastest solution in the company’s history. He expressed anticipation for NVIDIA’s release of the B100 and B200 chips. This news has sparked significant market interest, as NVIDIA has yet to publicly mention the B200 chip.

Clarke further stated that the B200 chip will showcase Dell’s engineering expertise in high-end servers, especially in liquid cooling systems. As for the progress of the B100 chip, NVIDIA has yet to disclose its specific parameters and release date.

NVIDIA’s current flagship H200 chip in the high-performance computing market adopts the Hopper GPU architecture paired with HBM3e memory chips, considered the most capable chip for AI computing in the industry.

However, NVIDIA continues to accelerate the development of its next-generation AI chip architectures. According to NVIDIA’s previously disclosed development roadmap, the next-generation product after the H200 chip is the B100 chip. Therefore, the expectation was that the B100 chip would be the highest-specification chip based on the Blackwell GPU architecture. Nevertheless, with the emergence of the B200 chip, it has sparked further speculation.

Previously, media speculation cited by the report from Commercial Times stated based on the scale of the H200 chip that the computational power of the B100 chip would be at least twice that of the H200 and four times that of the H100.

Read more

• [News] NVIDIA Expands Advanced Packaging Supply Chain with Intel’s Inclusion, Diverting Orders from TSMC
• [News] NVIDIA Reportedly Overwhelms TSMC with 3 and 4-Nanometer Orders

(Photo credit: NVIDIA)

The annual AI event, NVIDIA GTC (GPU Technology Conference), is set to take place on March 17th, as H200 and the next-generation B100 will reportedly be announced ahead of schedule to seize the market. According to Commercial Times’ report citing sources, H200 and the upcoming B100 will adopt TSMC’s 4-nanometer and 3-nanometer processes respectively. H200 is expected to be launched in the second quarter, while it’s rumored that orders for the B100 adopting Chiplet architecture have already been placed for production.

Sources cited by the report also indicate that NVIDIA’s orders are robust, pushing TSMC’s 3 and 4-nanometer production capacity to near full utilization, making the first quarter, traditionally a slow season, unexpectedly busy.

Regarding the matter of NVIDIA’s next-generation chip orders overwhelming TSMC’s advanced processes, TSMC stated that details regarding production capacity remain consistent with the previous earnings call and will not be elaborated further.

Still, Commercial Times further cited industry sources, revealing that TSMC, in response to anticipated capacity constraints by 2023, is accelerating its efforts. Particularly focusing on advanced packaging like CoWoS, they’ve not only relocated equipment from the Longtan facility but also swiftly activated the AP6 plant in Zhunan.

Another industry sources reportedly indicate that the planned construction of the Tongluo
facility, initially slated for the second half of this year, is now scheduled to commence in the second quarter. The aim is to ramp up 3D Fabric capacity to produce 110,000 12-inch wafers per month by the first half of 2027.

Meanwhile, TSMC’s advanced processes remain fully utilized, with capacity utilization exceeding 90% in February, driven by sustained AI demand.

NVIDIA, on the other hand, recently emphasized that computational-intensive tasks like Generative AI and large language models require multiple GPUs. From customer purchase to model deployment, it takes several quarters. Thus, this year’s inference applications stem from GPU purchases made last year. As model parameters grow, GPU demand is expected to expand.

In addition to increasing GPU quantities, NVIDIA’s GPU efficiency is poised for a significant boost this year. The Blackwell series, notably the B100, is hailed as NVIDIA’s next-generation GPU powerhouse by the market.

Not only is it the first to adopt TSMC’s 3-nanometer process, but it’s also the pioneer in Chiplet and CoWoS-L packaging among NVIDIA products. This tackles high power consumption and cooling issues, with projected single-card efficiency and transistor density expected to surpass AMD’s MI300 series set to debut in the first quarter.

Read more

• [News] NVIDIA Expands Advanced Packaging Supply Chain with Intel’s Inclusion, Diverting Orders from TSMC
• [News] NVIDIA CEO Jensen Huang Meets with TSMC Executives in Taiwan, Addressing the Significant AI Chip Shortage

(Photo credit: Kioxia)

South Korean memory giant SK Hynix is reportedly exploring a collaboration with Japanese NAND flash memory manufacturer Kioxia to produce High Bandwidth Memory (HBM) for AI applications, as per MoneyDJ citing Jiji Press.

According to Jiji Press’ report on March 1st, it is estimated that production will take place at the Japanese plant jointly operated by Kioxia and Western Digital (WD). Kioxia, on the other hand, will evaluate the proposed collaboration based on semiconductor market conditions and its relationship with WD.

The report highlights that HBM, a type of DRAM primarily used in AI servers, is experiencing a surge in demand worldwide, led by NVIDIA. Moreover, according to a previous TrendForce press release, the three major original HBM manufacturers held market shares as follows in 2023: SK Hynix and Samsung were both around 46-49%, while Micron stood at roughly 4-6%.

For SK Hynix, leveraging Kioxia’s existing plants in Kitakami, Iwate Prefecture, and Yokkaichi, Mie Prefecture, Japan, to produce HBM would enable the rapid establishment of an expanded production system.

Meanwhile, the joint-operated Japanese plants of Kioxia and WD currently only produce NAND Flash. If they were to produce the most advanced DRAM in the future, it would also contribute to Japan’s semiconductor industry revitalization plan.

The report further addresses that SK Hynix has indirectly invested approximately 15% in Kioxia through Bain Capital, a U.S.-based investment firm. Bain Capital is reportedly negotiating with SK Hynix behind the scenes, seeking to revive the Kioxia/WD merger. However, as per sources cited in Jiji Press’ report, “this collaboration and the merger are two separate discussion matters.”

According to a previous report from Asahi News on February 23, Kioxia and WD are expected to restart merger negotiations at the end of April. Although the merger negotiations between the two parties hit a roadblock last autumn, both are facing pressure to expand their scale for survival. However, whether the two parties can ultimately reach a merger agreement remains uncertain.

As per TrendForce’s  data for 3Q23, Samsung maintained its position as the top global NAND flash memory manufacturer, commanding a significant market share of 31.4%. Following closely, SK Group secured the second position with a 20.2% market share. Western Digital occupied the third position with a market share of 16.9%, while Japan’s Kioxia held a 14.5% market share.

Asahi News further indicates that if Kioxia and WD, the 2 companies which all manufacture NAND Flash products are to merge, their scale will rival that of the global market leader, Samsung Electronics.

The Japanese government reportedly views the Kioxia/WD merger as a “symbol” of Japan-US semiconductor cooperation and has provided support. However, the merger negotiations hit an impasse last fall, reportedly due to opposition from SK Hynix, indirectly invested in Kioxia.

Read more

• [News] NAND Flash Manufacturers Kioxia and WD Reportedly Set to Resume Merger Talks in Late April
• [News] Kioxia and Western Digital Resume Merger Negotiations? Rumors of Bain Negotiating with SK Hynix Surface

(Photo credit: Kioxia)

Intel’s foundry has extended its public roadmap, incorporating the Intel 14A process into the advanced process schedule and adding specific nodes. However, recent modifications to the roadmap have moved Intel 14A forward to 2026 and introduced a new process in 2027, namely 1 nanometer (Intel 10A).

According to TechNews citing reports from global media outlets tom’s Hardware and Extremetech, this marks Intel’s first announcement of the commencement of the 1-nanometer process. Although Intel had introduced Intel 10A at its exhibition, the news was restricted until now and has just been disclosed.

Intel 10A is set to enter the production/development (non-mass production) phase in 2027, while Intel 14A (1.4 nanometers) is scheduled for early production in 2026. Additionally, Intel is committed to constructing a fully autonomous AI-driven fab.

Keyvan Esfarjani, Intel’s Executive Vice President and General Manager of Manufacturing and Supply Chain, introduced the latest developments and showcased the technical roadmap. Intel plans to commence development of the 10A node by late 2027 to address gaps in EUV technology.

Assuming that Intel successfully launches its 1.8-nanometer process next year, follows with a 1.4-nanometer process in 2026, and then advances to 1-nanometer in 2027, Extremetech’s report claims that Intel is likely to be ahead of its competitor TSMC. TSMC estimates to begin its 2-nanometer process around 2025 or 2026, followed by a 1.4-nanometer process thereafter.

However, Intel has not disclosed any details regarding the 10A node, but it promises at least double-digit improvements in power consumption and performance. Intel CEO Pat Gelsinger has previously stated that new processes typically improve critical dimensions by approximately 14% to 15%. Therefore, it is plausible that the 10A and 14A nodes will also experience similar improvements.

Source: Intel

As per Intel’s roadmap, Intel 14A is also optimized in 2027, so it seems that 10A falls between 14A and 14A-E.

It is worth noting that according to Intel’s presentation notes, the final scale, speed, and process depend on commercial conditions and incentives, implying that funding from the U.S. Chip Act will affect expansion capacity.

Current Technological Developments at Intel

Intel’s 20A integrates two new technologies: backside power (PowerVIA) and GAA transistors (RibbonFET). Additionally, there is a proactive effort to enhance production capacity for advanced packaging technologies such as Foveros, EMIB, SiP (Silicon Photonics), and HBI (Hybrid Bond Interconnect).

Recently, Intel concluded all internal packaging for standard packaging, redirecting focus entirely towards high-end packaging, with standard packaging tasks now handled by OSATs (outsourced assembly and test companies).

While Intel’s 18A production base is located in Arizona, the location for manufacturing the 10A node has not been disclosed.

Read more

• [News] Intel Promotes 1.8-Nanometer Process in South Korea, Reportedly Pledges Various Benefits to Startups
• [News] Samsung Secures 2-Nanometer Order from Japanese AI Startup Preferred Networks

(Photo credit: Intel)