The world’s four major CSPs (Cloud Service Providers) – Microsoft, Google, Amazon, and META – are continuously expanding their AI infrastructure, with their combined capital expenditures projected to reach USD 170 billion this year. According to the industry sources cited in a report from Commercial Times, it’s pointed out that due to the surge in demand for AI chips and the increased area of silicon interposers, the number of chips that can be produced from a single 12-inch wafer is decreasing. This situation is expected to cause the CoWoS (Chip on Wafer on Substrate) production capacity under TSMC to remain in short supply.

Regarding CoWoS, according to TrendForce, the introduction of NVIDIA’s B series, including GB200, B100, B200, is expected to consume more CoWoS production capacity. TSMC has also increased its demand for CoWoS production capacity for the entire year of 2024, with estimated monthly capacity approaching 40,000 by the year-end, compared to an increase of over 150% from the total capacity in 2023. A possibility exists for the total production capacity to nearly double in 2025.

However, with NVIDIA releasing the B100 and B200, the interposer area used by a single chip will be larger than before, meaning the number of interposers obtained from a 12-inch wafer will further decrease, resulting in CoWoS production capacity being unable to meet GPU demand. Meanwhile, the number of HBM units installed is also multiplying.

Moreover, in CoWoS, multiple HBMs are placed around the GPU, and HBMs are also considered one of the bottlenecks. Industry sources indicate that HBM is a significant challenge, with the number of EUV (Extreme Ultraviolet Lithography) layers gradually increasing. For example, SK Hynix, which holds the leading market share in HBM, applied a single EUV layer during its 1α production phase. Starting this year, the company is transitioning to 1β, potentially increasing the application of EUV by three to four times.

In addition to the increased technical difficulty, the number of DRAM units within HBM  has also increased with each iteration. The number of DRAMs stacked in HBM2 ranges from 4 to 8, while HBM3/3e increases this to 8 to 12, and HBM4 will further raise the number of stacked DRAMs to 16.

Given these dual bottlenecks, overcoming these challenges in the short term remains difficult. Competitors are also proposing solutions; for instance, Intel is using rectangular glass substrates to replace 12-inch wafer interposers. However, this approach requires significant preparation, time, and research and development investment, and breakthroughs from industry players are still awaited.

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(Photo credit: NVIDIA)

As Apple keeps advancing in AI as well as developing its own in-house processors, industry sources indicated that the tech giant’s Chief Operating Officer (COO) Jeff Williams recently made a visit to TSMC, and was personally received by TSMC’s President, C.C. Wei, according a report by Economic Daily News.

The low-profile visit was made to secure TSMC’s advanced manufacturing capacity, potentially 2nm process, booked for Apple’s in-house AI-chips, according to the report.

Apple has been collaborating with TSMC for many years on the A-series processors used in iPhones. In recent years, Apple initiated the long-term Apple Silicon project, creating the M-series processors for MacBook and iPad, with Williams playing a key role. Thus, his recent visit to Taiwan has garnered significant industry attention.

Apple did not respond to the rumor. TSMC, on the other hand, has maintained its usual stance, not commenting on market speculations related to specific customers.

According to an earlier report from The Wallstreet Journal, Apple has been working closely with TSMC to design and produce its own AI chips tailored for data centers in the primary stage. It is suggested that Apple’s server chips may focus on executing AI models, particularly in AI inference, rather than AI training, where NVIDIA’s chips currently dominate.

Also, in a bid to seize the AI PC market opportunity, Apple’s new iPad Pro launched in early May has featured its in-house M4 chip. In an earlier report by Wccftech, Apple’s M4 chip adopts TSMC’s N3E process, aligning with Apple’s plans for a major performance upgrade for Mac.

In addition to Apple, with the flourishing of AI applications, TSMC has also reportedly beening working closely with the other two major AI giants, NVIDIA and AMD. It’s reported by the Economic Daily News that they have secured TSMC’s advanced packaging capacity for CoWoS and SoIC packaging through this year and the next, bolstering TSMC’s AI-related business orders.

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(Photo credit: TSMC)

In addition to the aggressive overseas expansion plans recently, TSMC also demonstrates its ambition of increasing specialty capacity, targeting to be expanded by 50% by 2027, according to a report by AnandTech. A key driver of this demand will be TSMC’s forthcoming specialty node, N4e, a 4nm-class ultra-low-power production node.

Citing Kevin Zhang, TSMC’s Senior Vice President of the Business Development and Overseas Operations Office, the report revealed that TSMC plans to expand its specialty capacity by up to 1.5 times in the next four to five years. To accomplish this goal, it would not only convert existing capacity, but construct new fab space dedicated to specialty processes.

TSMC offers a range of specialty nodes catering to various applications such as power semiconductors, mixed analog I/O, and ultra-low-power applications (e.g., IoT), according to the report. Currently, the semiconductor giant’s most advanced specialty node is N6e, a variant derived from N7/N6 that accommodates operating voltages ranging from 0.4V to 0.9V. With N4e, TSMC aims to support voltages below 0.4V.

According to the materials TSMC provided in its latest earnings call, in the first quarter, HPC accounted for 46% of its total revenue, while IoT-related and automotive applications accounted for 6% of its total revenue, respectively. All the applications mentioned above are closely connected to specialty nodes.

TSMC’s overseas expansion plans are also closely related to its focus on specialty nodes. At the grand opening of JASM’s first Kumamoto plant in February, TSMC Chairman Mark Liu stated that JASM would use the latest green manufacturing practices to produce best-in-class specialty semiconductor technology.

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(Photo credit: TSMC)

Previously, the U.S. Department of Commerce revoked Intel and Qualcomm’s export licenses to Huawei, leading to speculation that they are now prohibited from collaborating with Huawei. According to a report from TechNews, Qualcomm anticipates that after 2024, it will no longer receive product revenue from Huawei but will continue to collect patent royalties.

As per a report from global media outlet tom’s Hardware, on May 7, 2024, the U.S. Department of Commerce informed Qualcomm that it was revoking the company’s license to export 4G and certain other integrated circuit products, including Wi-Fi products, to Huawei. a nd its affiliates and subsidiaries, effective immediately.Consequently, Qualcomm expects no product revenue from Huawei after this year.

According to TechNews, while Qualcomm used to provide processors to Huawei for use in its smartphones, Huawei’s HiSilicon division has developed its own chipsets, Kirin 9000 and 9010, therefore barely needing the support from Snapdragon processors.

Qualcomm reportedly noted in another statement that Huawei has recently launched new 5G-supported devices using its own IC products. Although Qualcomm can still sell IC products to Huawei under the current license, it does not expect to receive any product revenue from Huawei after this year.

Despite having its own processors, Huawei lacks the alternative for Intel’s Core or Xeon CPUs from PCs and servers, and will likely continue using them for the foreseeable future, according to tom’s Hardware. Meanwhile, Qualcomm may continue to collect patent royalties from Huawei and other Chinese smartphone manufacturers.

Qualcomm also mentioned that it has recently extended, renewed, or signed licensing agreements with several major OEMs. Negotiations are ongoing with key OEMs, including Huawei, for agreements set to expire at the beginning of fiscal year 2025.

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(Photo credit: Qualcomm)

On May 16, Japanese foundry startup Rapidus announced the signing of a Memorandum of Understanding (MoU) with American RISC-V architecture chip design company, Esperanto. The two sides will collaborate on the research and development of AI semiconductors for data centers, aiming to jointly develop low-power AI chips.

Currently, according to a report from DRAMeXchange, despite the gradual ease of GPU shortage, power supply has become another bottleneck in the course of the AI development.

Industry sources cited in the report have pointed out that CPU and GPU have played a critical role in fostering the prosperity of the AI market. However, the increasing power consumption of the latest chips is causing a recent crisis. For instance, it is expected that by 2027, the energy consumed by generative AI processing will account for nearly 80% of the total electricity consumption of data centers in the United States.

Data center is a major engine to drive the growth of electricity demand. With the advent of the AI era, represented by generative AI, the power required for high-performance computing chips continuously increases, which in turn raises the electricity consumption of data centers.

Esperanto has been committed to designing large-scale parallel, high-performance, and energy-efficient computing solutions. Previously, it launched the ET-SOC-1-based RISC-V architecture many-core AI/HPC acceleration chip, built on TSMC’s 7nm process.

Rapidus is a wafer foundry founded in August 2022 with joint investments from eight Japanese companies, including Toyota, Sony, NTT, NEC, SoftBank, Denso, NAND flash giant Kioxia, and Mitsubishi UFJ. Its first factory, “IIM-1,” based in Chitose, Hokkaido, already broke ground in September 2023 and is expected to start running trial production lines in April 2025 and install EUV lithography machines. Rapidus aims to mass-produce the most advanced logic chips below 2nm by 2027.

The initial focus of the cooperation between Rapidus and Esperanto is to enable future semiconductor designers to develop more energy-efficient solutions for AI inference and high-performance computing workloads in data centers and enterprise edge applications. This will help mitigate the unsustainable growth of energy consumption across global data centers.

In 2022, data center, AI, and cryptocurrency consumed about 460 TWh of electricity worldwide in total, comprising 2% of the overall global demand. The International Energy Agency (IEA) predicts that, influenced by factors such as generative AI, global data center power demand could rise to about 1,000 TWh in 2026, roughly equivalent to the entire electricity consumption in Japan.

IEA states that updated regulations and technological improvements, including energy efficiency, are of great significance to curb the surge in data center energy consumption.

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(Photo credit: Rapidus)