As Intel’s January announced the collaboration with UMC on the 12-nanometer process platform, UMC’s Co-General Manager, Jason Wang, led a team to support Intel’s IFS event.

Cited by Commercial Times in its report, Wang emphasized that UMC’s existing customers would have more production location options and benefit from the platform strategy. UMC will seamlessly transition from the 28/22-nanometer to the critical 12-nanometer.

Followed by joint interviews to share insights into the future strategies of both parties, Wang stated that in the face of rapid changes and challenges in the external environment, industries need to strengthen their cooperative relationships and seize opportunities for collaboration.

Intel and UMC announced their collaboration at the end of January, focusing on the development of a shared platform for the 12-nanometer process. In the future, UMC will be able to expand its orders for the front-end of the 12-nanometer process, while Intel will secure orders for the 12-nanometer wafer manufacturing.

Jason Wang emphasized that UMC has a comprehensive solution for the 28/22-nanometer, with demand trending towards stability. However, due to past limitations in resource allocation , UMC has paused at the 14/16-nanometer. Advancing to more advanced processes is just a matter of timing.

Wang further stated that both parties will focus on creating customer value, breaking frameworks, and innovating in cooperation. The two companies complement each other’s strengths, accelerating the timeline for technological development and expanding their global footprint.

Wang revealed that Intel has already included UMC’s 12-nanometer process in its product roadmap and has begun deep collaboration. UMC has deployed personnel to oversee this, with Intel leveraging UMC’s know-how in management.

Additionally, the collaboration involves revenue sharing rather than the rumored licensing fees. They anticipate completing the Process Design Kit (PDK) by next year and achieving mass production by the end of 2026.

Overall, TrendForce views this alliance as a significant step. UMC brings its plentiful experience in mature processes, while Intel contributes its advanced technological prowess.

This partnership is not just about mutual benefits at the 10nm process level; it’s a watchpoint for potentially deeper and more extensive collaboration in their respective fields of expertise. In the dynamic world of semiconductor manufacturing, this Intel-UMC alliance is a fascinating development to keep an eye on.

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(Photo credit: Intel)

Pat Gelsinger, CEO of Intel, announced on February 22nd that Intel will expand its orders to TSMC, as per a report by Commercial Times.

Following the IFS Direct Connect event in San Jose, USA, Gelsinger pointed out in an interview that two generations of CPU Tiles would be manufactured using TSMC’s N3B process,  marking the official arrival of Intel CPU orders for laptop platforms. 

Gelsinger’s interview confirms that Intel has indeed expanded its outsourcing orders to TSMC. Currently, TSMC is responsible for producing Intel CPUs, GPUs, and NPUs tiles for the Arrow and Lunar Lake platforms.

As per Intel’s product roadmap, Arrow Lake will utilize the Intel 20A process, while Lunar Lake will utilize the 18A process, both incorporating transistor designs such as PowerVia and RibbonFET.

Gelsinger previously stated that Intel Foundry is striving to become the world’s second-largest foundry by 2030. The objective is to fill the fabs and supply the widest range of customers globally, including competitors like NVIDIA and AMD.

According to TrendForce’s data statistics for the third quarter of 2023, the world’s top three foundries were TSMC, Samsung, and GlobalFoundries, with Intel Foundry Services (IFS) ranking ninth at the time.

As for rumors about the US government considering providing over USD 10 billion in subsidies, he disclosed that they expect to receive chip legislation subsidies very soon, although the exact amount is yet to be announced.

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(Photo credit: Intel)

Kevin Zhang, Senior Vice President of Business Development at TSMC, introduced the company’s latest technologies at the International Solid-State Circuits Conference (ISSCC) 2024. According to TechNews citing from the speech, Zhang shared insights into future technological advancements, prospects for advanced processes, and the latest semiconductor technologies needed in various fields.

Zhang noted that since the introduction of ChatGPT and Wi-Fi 7, a lot of advanced semiconductor are required, as we are entering an accelerated growth period for semiconductor going forward.

In the automotive sector, the industry is undergoing a revolution, with many suggesting that new vehicles will be software-defined. However, Zhang believes it’s more about silicon-defined because software needs to run on silicon, driving the future of autonomous driving capabilities.

CFET (Complementary Field-Effect Transistor)

In terms of technology, Transistor remain at the heart of the innovation, silicon innovation. It has shifted from geometry reduction to architectural innovation and the use of new materials. Moving from 16-nanometer FinFET to today’s 2-nanometer Nano Sheet technology represents significant progress in high-performance computing and architectural innovation.

What’s next? The answer is CFET.

Kevin Zhang explained that CFET involves stacking nMOS and pMOS on top of each other, significantly improving component currents and increasing transistor density by 1.5 to 2 times.

Alternatively, efforts are being made to create higher-performance switching devices from low-dimensional materials such as 2D materials, surpassing today’s devices or transistors.

Kevin Zhang also showcased that TSMC has successfully fabricated CFET architectures in the laboratory, stating, “This is a real integrated device that has been fabricated in our lab. Here, you see the transistor IV curve. They are beautiful curves. So, this is a significant milestone in terms of continuing to drive the innovation of the transistor architecture.”

However, as the geometry of the transistor shrinks, it becomes increasingly difficult and costly. This necessitates collaboration between process development teams and design research to achieve optimal benefits, known as “Design-Technology Co-Optimization” (DTCO).

In addition, TSMC has introduced FINFLEX technology, enabling chip designers to choose and mix the best fin structures to support each critical functional block, achieving optimal performance, density, and power consumption.

Another example of DTCO is Static Random Access Memory (SRAM). SRAM has scaled from 130 nanometers to the current 3 nanometers, and TSMC has achieved a over 100x density improvement, a result of collaboration or combination of a process innovation and adoption of the more advanced design technique.

Nevertheless, the essence or the objective of this technology scaling is for “energy efficient compute,” as Kevin Zhang expressed. He stated that in the entire semiconductor industry, TSMC has come a long way, and this progress has made today’s AI possible.

• Advancements in HPC/AI Technology Platforms: 3D Stacking, Silicon Photonics, CPO

Whether it’s GPUs, TPUs, or customized ASICs, they all feature this particular integration scheme. Currently, the mainstream is 2.5D packaging. However, to meet future high-performance computing demands, this platform needs significant enhancement, requiring higher density and lower power consumption computation.

Therefore, stacking is needed, including integrating many memory bandwidths and HBM into the package, while considering issues such as power supply, I/O, and interconnect density.

Consequently, Kevin Zhang stated that bringing “silicon photonics into packaging” is the future direction. However, this will face many challenges, such as Co-Packaged Optics (CPO) closer to the electronic side.

1. 3D Stacking

When it comes to 3D stacking, Kevin Zhang presented a diagram and explained that to achieve higher interconnect density, specifically Chip-to-Chip connections, 3D stacking allows the bonding pitch to scale to just a few micrometers, achieving interconnect density like monolithic. “That’s why the 3D (stacking) is the future,” he concluded.

2. Silicon Photonics / Co-Packaged Optics (CPO)

Kevin Zhang pointed out that while electronics excel at computation, photons are better for signaling or communication. He illustrated that if a 50 terabyte switch, an all-electronic copper system were used, it would consume 2,400 W.

The current solution involves using pluggable modules, which can save 40% of power (> 1500W). However, as the need for higher-speed signals and larger bandwidths increases in the future, this solution falls short. Therefore, integrating silicon photonics technology is necessary to introduce photon capabilities.

• Automotive Technology

1. Pursuing Low DPPM

Fundamentally, the latest automotive technologies require significant computational power, but power consumption is becoming a concern, especially for battery-powered vehicles.

Kevin Zhang states that automotive semiconductor technology has lagged behind consumer or HPC technologies by several generations due to stringent safety requirements. The DPPM (Defects Per Million) for automotive applications must be close to zero.

Therefore, fabs, semiconductor manufacturers, and automotive designers must collaborate more closely to accelerate this pace. He also promises, “you will see 3 nanometer in your car before long.”

2. MRAM/RRAM

As automotive transitions to a domain architecture, MCUs (Microcontroller Units) become increasingly important and require advanced semiconductor technology to provide computational capabilities.

Traditional MCUs mostly rely on floating-gate technology, but this technology encounters bottlenecks below 28 nanometers. Fortunately, the industry has invested in new memory technologies, including new non-volatile memories such as Magnetic Random Access Memory (MRAM) or Resistive Random Access Memory (RRAM).

Therefore, transitioning from MCU to MRAM or RRAM-based technologies helps drive continuous technology scaling from 28 nanometers to 16 nanometers, or even 7 nanometers.

• Sensor and Display: CIS (CMOS Image Sensors)

Sensor technology has evolved from simple 2D designs and single layer design to intelligent systems with 3D wafer stacking, essentially layering the signal processing on top of the sensing layer.

Kevin Zhang also mentioned, “our technologies already start investing, researching on the multi-layer design.”

Engaging in three or more layer designs allows for the optimization of pixels, continuing the trend of scaling pixel sizes while meeting resolution requirements and achieving optimal sensing capabilities simultaneously.

Another example is AR (Augmented Reality) and VR (Virtual Reality), where separating memory layers and stacking them onto other logic chips can effectively reduce size while maintaining high-performance demands.

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(Photo credit: TSMC)

On February 21st, Intel Foundry Direct Connect 2024 took place in San Jose, USA. During the conference, Intel announced the launch of Intel Foundry, a system-level foundry tailored for the AI era. They unveiled seven new process nodes beyond 2024, including the next-generation Intel 14A and 14A-E processes, which utilize High-NA EUV equipment.

In the reconstruction of Intel, Gelsinger had also articulated a vision to establish a world-class foundry and become a major chip capacity provider in the United States and Europe. Now, three years later, this vision is becoming a reality.

The newly introduced Intel Foundry is a rebranded and restructured organizational model. Gelsinger emphasizes that Intel is not merely fixing a company but “establishing two vibrant new organisations”: Intel Foundry and Intel Products. Intel Foundry is dedicated to serving both internal and external customers on a large scale, establishing a supply chain to ensure capacity.

Gelsinger stated that Intel Foundry is striving to become the world’s second-largest foundry by 2030. According to TrendForce’s data statistics for the third quarter of 2023, the world’s top three foundries were TSMC, Samsung, and GlobalFoundries, with Intel Foundry Services (IFS) ranking ninth at the time.

• Process Innovation

During the conference, Intel expanded its process technology roadmap, introducing the evolution versions of Intel 14A and several specialized nodes.

Intel also confirmed that its “Four Years, Five Process Nodes” roadmap is progressing steadily, and it will be the first to offer backside power delivery solutions in the industry. Intel expects to regain process leadership by 2025 with the Intel 18A process node.

The new roadmap includes evolved versions of Intel 3, Intel 18A, and Intel 14A technologies. For instance, Intel 3-T is optimized for 3D advanced packaging designs through silicon via technology and is expected to be production-ready soon.

Intel also highlighted its progress in mature process nodes, such as the newly announced 12-nanometer node developed in collaboration with UMC in January.

Regarding this collaboration, TrendForce believes that this partnership, which leverages UMC’s diversified technological services and Intel’s existing factory facilities for joint operation, not only aids Intel in transitioning from an IDM to a foundry business model but also brings a wealth of operational experience and enhances manufacturing flexibility.

Intel’s foundry plans to introduce a new node every two years and evolve node versions along the way, helping customers improve their products through Intel’s leading process technology.

Source: Intel

Additionally, Intel Foundry announced the addition of FCBGA 2D+ in the technical portfolio of Intel Foundry Advanced System Packaging and Testing (Intel Foundry ASAT). This combination will include FCBGA 2D, EMIB, Foveros, and Foveros Direct technologies.

• Microsoft Becomes Intel’s 18A New Client

Intel’s client have reportedly expressed support for Intel’s systemic foundry services. Satya Nadella, Chairman and CEO of Microsoft, announced during the Intel Foundry Direct Connect conference that Microsoft plans to utilize Intel’s 18A process to manufacture a chip designed by the company.

Satya Nadella stated, “We are in the midst of a very exciting platform shift that will fundamentally transform productivity for every individual organization and the entire industry.”

Nadella further mentioned, “To achieve this vision, we need a reliable supply of the most advanced, high-performance and high-quality semiconductors. That’s why we are so excited to work with Intel Foundry, and why we have chosen a chip design that we plan to produce on Intel 18A process.”

Intel Foundry has amassed a substantial number of client design cases across various processes, including Intel 18A, Intel 16, and Intel 3, as well as Intel Foundry ASAT, which encompasses advanced packaging.

Overall, the anticipated lifetime deal value for Intel Foundry in wafer manufacturing and advanced packaging surpasses USD 15 billion.

• IP and EDA Suppliers

IP (Intellectual Property) and EDA (Electronic Design Automation) partners Synopsys, Cadence, Siemens, Ansys, Lorentz, and Keysight have announced that tools and IP are ready to help foundry customers accelerate advanced chip designs based on Intel’s 18A process, featuring the industry-first backside power delivery solution. Furthermore, these partners have confirmed the availability of their EDA and IP solutions across various Intel node families.

Additionally, several suppliers have announced plans to collaborate on assembly technologies and design flows for Intel’s EMIB 2.5D packaging technology. These EDA solutions will ensure Intel can swiftly develop and deliver advanced packaging solutions to its customers.

Intel has also unveiled the “Emerging Business Initiative” (EBI), which involves collaboration with Arm to provide advanced foundry services for System-on-Chip (SoCs) based on the Arm architecture. This initiative aims to support startups in developing technology based on the Arm architecture by offering essential IP, manufacturing support, and financial assistance. It provides an important opportunity for both Arm and Intel to foster innovation and development in the industry.

• Systematic Foundry

Intel’s system-level foundry model offers optimization from factory networks to software. Intel and its ecosystem provide continuously improving technologies, reference designs, and new standards, enabling customers to innovate at the system level.

Stuart Pann, Senior Vice President of Intel Foundry, stated, “We are offering a world-class foundry, delivered from a resilient, more sustainable and secure source of supply, and complemented by unparalleled systems of chips capabilities. Bringing these strengths together gives customers everything they need to engineer and deliver solutions for the most demanding applications.”

• Global, Resilient, More Sustainable, and Trustworthy Systematic Foundry

In terms of sustainability, Intel aims to be the leading foundry in the industry. In 2023, Intel’s global factories achieved a preliminary estimate of a 99% renewable energy usage rate.

At the Intel Foundry Direct Connect conference, Intel reiterated its commitment to reaching 100% renewable energy usage, water positive status, and zero landfill waste by 2030. Additionally, Intel emphasized its commitment to achieving net-zero Scope 1 and Scope 2 greenhouse gas (GHG) emissions by 2040 and net-zero upstream emissions of Scope 3 GHG by 2050.

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(Photo credit: Intel)

NVIDIA, a global AI chip giant, has released its financial report on February 21st, surpassing profit and sales expectations with a remarkable 265% revenue growth, marking a historic high. Moreover, the company anticipates revenue for the current quarter to exceed expectations.

NVIDIA Announces Fourth Quarter Revenue of USD 22.1 billion, exceeding expectations of USD 20.62 billion. As per data from the London Stock Exchange Group (LSEG), adjusted earnings per share for the fourth quarter stand at USD 5.16, surpassing expectations of USD 4.64 per share.

Furthermore, NVIDIA anticipates sales of USD 24 billion for the current quarter. Analysts of LSEG project earnings per share of USD 5.00 and sales of USD 22.17 billion. Net profit for the quarter amounts to USD 12.29 billion, or USD 4.93 per share, marking a 769% increase from the same period last year, when it was USD 1.41 billion, or USD 0.57 per share.

NVIDIA attributed its 265% revenue growth compared to a year ago to robust sales of server artificial intelligence chips, especially its “Hopper” chips like the H100.

According to reports cited by Liberty Times Net, NVIDIA CEO Jensen Huang, during a conference call with industry analysts, addressed concerns among investors about the company’s ability to sustain this level of growth or sales throughout the year.

Huang told analysts that, ‘Fundamentally, the conditions are excellent for continued growth’ in 2025 and beyond.  He further cited strong underlying conditions driven by generative AI and a broader industry trend shifting toward accelerators of NVIDIA. This shift is expected to maintain high demand for the company’s GPUs.

Previously, as reported by Economic Daily News, when discussing the major trends in AI, Huang pointed out that AI will operate in smartphones, computers, robots, automobiles, as well as in the cloud and data centers. Huang emphasized that NVIDIA is a pioneer in accelerating computation and AI computing, and in the next decade, he envisions a reshaping of computation, with every industry being impacted.

Analysts cited in the report from Liberty Times Net anticipate that major supplier TSMC’s capacity expansion in advanced packaging in the first half of the year will help NVIDIA overcome core supply bottlenecks and provide more chips to customers.

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(Photo credit: NVIDIA)