Paul de Bot, President of TSMC Europe, confirmed during a seminar in the Netherlands on May 14th that TSMC will start construction of its first chip plant in Europe in Dresden, eastern Germany. The project is scheduled to commence in the fourth quarter of this year, with production expected to begin in 2027.

Last August, TSMC announced the joint venture factory project in Germany, with a total investment of USD 11 billion. Apart from TSMC, Infineon, NXP, and Bosch each holds a 10% stake.

According to a report from Reuters, Kevin Zhang, Senior Vice President of Business Development and Overseas Operations Office at TSMC, stated that the project has received strong support from the European Union and the German government, thus TSMC is confident in obtaining subsidies under the European Chips Act.

Kevin Zhang stated that the semiconductor ecosystem in Europe is currently exciting, indicating that setting up a foundry in Germany would allow TSMC to directly access its major automotive customers.

It is understood that TSMC’s fab in Germany will initially focus on the 22-nanometer process, mainly producing automotive microcontrollers. There is a possibility of expanding to produce more advanced chips in the future.

In addition, Intel, another semiconductor giant, had also planned a significant investment of EUR 30 billion for constructing two new fabs in Magdeburg, Eastern Germany.

TSMC’s global expansion has reached locations in China, the United States, Japan, and Germany, solidifying its goal of being a “long-term and trustworthy provider of technology and capacity.”

TSMC’s Kumamoto Plant in Japan held its opening ceremony in February, with mass production expected to begin in the fourth quarter. Kevin Zhang also emphasized that TSMC will continue to expand its operations in Japan.

In response to growing customer demand, TSMC announced in February plans to begin construction of its Kumamoto Fab 2 by the end of the year, which will be its second, more advanced fab in Japan, scheduled to start operations by the end of 2027.

In contrast, the construction progress of its Arizona plant in the United States has been relatively slow. Due to the delay in the first phase’s production timeline from the end of 2024 to the first half of 2025, the production schedule for the second phase will also be postponed to start after 2027.

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Google reportedly collaborates with Samsung as its foundry partner for Tensor G4 in the Pixel 9 lineup, which is anticipated to hit the market later this year. However, the tech giant may possibly turn to TSMC in Pixel 10, using the latter’s 3nm node for Tensor G5, according to a report by Wccftech.

It is reported that, to facilitate this transition, Google has expanded its Taiwanese R&D center, enabling closer collaboration with TSMC to produce its most advanced silicon. In late April, Google opened its second hardware office in Taiwan for Pixel, Fitbit, and Nest development, located at the TPark campus in New Taipei City.

Wccftech stated that Google has changed its stance, as Tensor G3’s performance lags behind its competitors, and TSMC might help to resolve the problem. Tensor G3, manufactured utilizing Samsung’s 4LPP node, is reported to lag behind in CPU performance, if compared with Qualcomm’s Snapdragon 8 Gen2 and Apple’s A17 Pro.

The aforementioned report suggested that Google plans to utilize TSMC’s 3nm ‘N3E’ process for its advanced chipset, the same node employed in Apple’s M4 chips that power the latest iPad Pro models.

At the Google I/O 2024 developer conference on May 14th, Google unveiled its 6th generation custom chip, the Trillium TPU, rumored to be manufactured on a TSMC 3nm or 4nm process, according to a report by CTEE. It is also reported that Google has been aggressively working on its upcoming TPU models, collaborating with Taiwanese fabless companies MediaTek and Alchip. Taiwan’s largest PCB substrate manufacturer, Unimicron, is also said to be included in the Trillium TPU’s supply chain.

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• [News] Google Unveils 6th Generation TPU, Scheduled to Launch Later This Year

(Photo credit: TSMC)

According to a report from global media outlet Wccftech, China’s largest foundry, SMIC, is rumored to produce 5-nanometer chips for Huawei this year, without the need for extreme ultraviolet (EUV) lithography machines manufactured by Dutch company ASML.

As per a report by Businesskorea, SMIC seems to be able to use old deep ultraviolet (DUV) lithography machines purchased before the sanctions were implemented to manufacture 5-nanometer chips. However, this would incur higher costs and could also affect yields.

Previously reported by the Financial Times, industry sources have indicated that SMIC’s prices for 5-nanometer and 7-nanometer processes are 40% to 50% higher than TSMC’s, and the yield less than one-third of TSMC’s. Later, it was estimated that SMIC’s 5nm chip prices would be up to 50 percent more expensive than TSMC’s on the same lithography, meaning that Huawei would face a tough time selling its Mate 70 series to consumers with a decent margin if it attempts to absorb a majority of those component costs.

Huawei was previously said to be working closely with its local foundry partner to introduce a new Kirin SoC that will be found in the upcoming Mate 70 series, scheduled to be released in October, with SMIC’s 5nm process has been said completed and is ready to mass produce the first batch of wafer.

This means that if Huawei attempts to absorb most of these costs, it will face the challenge of insufficient profit margins when selling the Mate 70 series to consumers. The tech giant may attract customers by promoting its in-house HarmonyOS Next, which is reportedly set to debut with the Mate 70 series. The model is said to be equipped with better efficiency in memory management compared to Google’s Android platform, according to Wccftech.

Meanwhile, Intel has recently secured its supply of the new High-NA EUV (high-numerical aperture extreme ultraviolet) lithography equipment from ASML, which the semiconductor heavyweight will allegedly use on its 18A (1.8nm) and 14A (1.4nm) nodes, according to a report from TheElec.

On the other hand, according to sources cited by a report from Economic Daily News, TSMC’s A16 advanced process node might not necessarily require ASML’s latest advanced chip manufacturing equipment, the High Numerical Aperture Extreme Ultraviolet Lithography (High-NA EUV), due to its expensive price.

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• [News] How Costly is the High-NA EUV? TSMC Reportedly Shocked, Considering Not Using the Equipment in its A16 Node
• [News] Intel Secures First Batch of High-NA EUV Equipment from ASML, Ahead of Samsung and SK Hynix

(Photo credit: SMIC)

According to sources and documents cited in a report from Reuters, two major Chinese chip manufacturers are in the early stages of producing High Bandwidth Memory (HBM) semiconductors, primarily for AI chipsets. Despite facing export restrictions from the United States, China is currently making progress mainly on older versions of HBM, gradually reducing reliance on other global suppliers.

Sources cited in the same report revealed that China’s largest DRAM chip manufacturer, ChangXin Memory Technologies (CXMT), is collaborating with chip packaging and testing company Tongfu Microelectronics to develop HBM chip samples, which are being showcased to potential customers.

On the other hand, Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. (XMC) is constructing a 12-inch plant with a monthly capacity of 3,000 wafers, which is planned to  manufucture HBM chips. Per the corporate registration documents, the plant is expected to commence operations in February this year.

Sources in the report mentioned that CXMT and other Chinese chip companies regularly hold meetings with semiconductor equipment manufacturers from South Korea and Japan to purchase tools for HBM development. Currently, CXMT, Tongfu Microelectronics, and XMC have not responded to these reports.

CXMT and XMC are both private companies that have received funding from local governments in China to drive technological development amid the country’s vigorous efforts to develop its semiconductor industry.

There also are reports indicating that Huawei, the Chinese tech giant subject to US sanctions, looks to collaborate with other local companies to produce HBM2 chips by 2026. According to a report from The Information, a group led by Huawei aimed at producing HBM chips includes Fujian Jinhua Integrated Circuit.

As per market reports cited by Reuters, China’s current focus is on HBM2. While the US has not restricted the export of HBM chips, HBM3 chips are manufactured using US technology, which many Chinese companies, including Huawei, are prohibited from using.

According to the analysis by Trendforce, the research and manufacturing of HBM involve complex processes and technical challenges, including wafer-level packaging, testing technology, design compatibility, and more. CoWoS is currently the mainstream packaging solution for AI processors, and in AI chips utilizing CoWoS technology, HBM integration is also incorporated.

CoWoS and HBM involves processes such as TSV (Through-Silicon Via), bumps, microbumps, and RDL (Redistribution Layer). Among these, TSV accounts for the highest proportion of the 3D packaging cost of HBM, close to 30%.

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• [News] XMC Initiates IPO Plan, Potentially Becoming China’s First HBM Foundry
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(Photo credit: CXMT)

At the Google I/O 2024 developer conference on Tuesday, Google unveiled its 6th generation custom chip, the Trillium TPU, which is scheduled to hit the market later this year, according to the report by TechCrunch.

According to the information provided by Google on its website, compared to TPU v5e, Trillium boasts a 4.7x peak compute performance increase per chip. Google has also doubled the High Bandwidth Memory (HBM) capacity and bandwidth, along with a 1x increase in Interchip Interconnect (ICI) bandwidth between chips.

Additionally, Trillium features the third-generation SparseCore, a dedicated accelerator for processing large embeddings, aimed at handling advanced ranking and recommendation workloads. Moreover, Trillium achieves a 67% higher energy efficiency compared to TPU v5e.

Trillium has the capacity to expand up to 256 TPUs within a singular pod boasting high bandwidth and low latency. Additionally, it incorporates multislice technology, allowing Google to interlink thousands of chips, thus constructing a supercomputer capable of facilitating a data center network capable of processing petabits of data per second.

In addition to Google, major cloud players such as AWS, Meta, and Microsoft have also made their way to develop their own AI Chips.

In late 2023, Microsoft unveiled two custom-designed chips, the Microsoft Azure Maia AI Accelerator, optimized for AI tasks and generative AI, and the Microsoft Azure Cobalt CPU, an Arm-based processor tailored to run general purpose compute workloads on the Microsoft Cloud. The former is reportedly to be manufactured using TSMC’s 5nm process.

In May 2023, Meta also unveiled the Meta Training and Inference Accelerator (MTIA) v1, its first-generation AI inference accelerator designed in-house with Meta’s AI workloads in mind.

AWS has also jumped into the AI chip market. In November, 2023, AWS released Trainium2, a chip for training AI models.

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(Photo credit: Google)