The US-China tech conflict has extended to RISC-V chips. Reuters reported on April 24th that the US Department of Commerce, in a letter dated around April 15th to members of Congress, highlighted concerns regarding China’s involvement in open-source RISC-V chip technology.

The Department of Commerce is reportedly assessing the potential national security risks associated with this and evaluating whether appropriate actions within its authority can effectively address any concerns.

According to the same report, the US Department of Commerce has emphasized in its letter the need for caution to avoid harming US companies participating in international organizations related to RISC-V technology. Previously, measures shifting control of 5G technology to China have posed obstacles for US companies in international standard-setting bodies (where China is also involved), thereby threatening America’s leadership position in the field.

RISC-V is an open-source architecture independent of the ARM architecture controlled by the UK-based semiconductor design company Arm, as well as the x86 architecture developed by the US chip giant Intel. RISC-V is utilized in various products, including smartphone chips and advanced processors for AI, making it a crucial component in the industry.

In an effort to break through US technology restrictions, China is reportedly placing significant emphasis on RISC-V technology. This has turned RISC-V into a new battleground in the US-China technology conflict.

As early as October 2023, Chairman Michael McCaul of the House Foreign Affairs Committee pointed out that China is abusing RISC-V to circumvent America’s dominant position in intellectual property required for chip design. McCaul cautioned against supporting China’s technology transfer strategy, as it would weaken US export control laws.

Regarding China’s promotion of RISC-V technology, Republican Senator Marco Rubio has warned that if the US does not expand export controls to address this threat, China could one day surpass the US and become the global leader in chip design.

Rubio’s statement underscores concerns within the US government about the strategic implications of China’s efforts to advance its semiconductor capabilities using technologies like RISC-V. The potential for China to gain a competitive edge in this critical sector is viewed as a significant national security issue by some US policymakers.

Read more

• [News] Arm’s Former CEO Engages in RISV-V Market
• [News] U.S. Department of Commerce Claims Huawei Chips Not as Advanced, Lag Behind U.S. Chips by Several Years

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TSMC today unveiled its newest semiconductor process, advanced packaging, and 3D IC technologies for powering the next generation of AI innovations with silicon leadership at the Company’s 2024 North America Technology Symposium.

TSMC debuted the TSMC A16TM technology, featuring leading nanosheet transistors with innovative backside power rail solution for production in 2026, bringing greatly improved logic density and performance. TSMC also introduced its System-on-Wafer (TSMC-SoW™) technology, an innovative solution to bring revolutionary performance to the wafer level in addressing the future AI requirements for hyperscaler datacenters.

“We are entering an AI-empowered world, where artificial intelligence not only runs in data centers, but PCs, mobile devices, automobiles, and even the Internet of Things,” said TSMC CEO Dr. C.C. Wei. “At TSMC, we are offering our customers the most comprehensive set of technologies to realize their visions for AI, from the world’s most advanced silicon, to the broadest portfolio of advanced packaging and 3D IC platforms, to specialty technologies that integrate the digital world with the real world.”

New technologies introduced at the symposium include:

TSMC A16TM Technology: With TSMC’s industry-leading N3E technology now in production, and N2 on track for production in the second half of 2025, TSMC debuted A16, the next technology on its roadmap.

A16 will combine TSMC’s Super Power Rail architecture with its nanosheet transistors for planned production in 2026. It improves logic density and performance by dedicating front-side routing resources to signals, making A16 ideal for HPC products with complex signal routes and dense power delivery networks.

Compared to TSMC’s N2P process, A16 will provide 8-10% speed improvement at the same Vdd (positive power supply voltage), 15- 20% power reduction at the same speed, and up to 1.10X chip density improvement for data center products.

TSMC NanoFlexTM Innovation for Nanosheet Transistors: TSMC’s upcoming N2 technology will come with TSMC NanoFlex, the company’s next breakthrough in design-technology co optimization. TSMC NanoFlex provides designers with flexibility in N2 standard cells, the basic building blocks of chip design, with short cells emphasizing small area and greater power efficiency, and tall cells maximizing performance. Customers are able to optimize the combination of short and tall cells within the same design block, tuning their designs to reach the optimal power, performance, and area tradeoffs for their application.

N4C Technology: Bringing TSMC’s advanced techynology to a broader range of of applications, TSMC announced N4C, an extension of N4P technology with up to 8.5% die cost reduction and low adoption effort, scheduled for volume production in 2025.

N4C offers area-efficient foundation IP and design rules that are fully compatible with the widely-adopted N4P, with better yield from die size reduction, providing a cost-effective option for value-tier products to migrate to the next advanced technology node from TSMC.

CoWoS, SoIC, and System-on-Wafer (SoW): TSMC’s Chip on Wafer on Substrate (CoWoS) has been a key enabler for the AI revolution by allowing customers to pack more processor cores and high-bandwidth memory (HBM) stacks side by side on one interposer. At the same time, our System on Integrated Chips (SoIC) has established itself as the leading solution for 3D chip stacking, and customers are increasingly pairing CoWoS with SoIC and other components for the ultimate system-in-package (SiP) integration.

With System-on-Wafer, TSMC is providing a revolutionary new option to enable a large array of dies on a 300mm wafer, offering more compute power while occupying far less data center space and boosting performance per watt by orders of magnitude.

TSMC’s first SoW offering, a logic only wafer based on Integrated Fan-Out (InFO) technology, is already in production. A chip-on-wafer version leveraging CoWoS technology is scheduled to be ready in 2027, enabling integration of SoIC, HBM and other components to create a powerful wafer-level system with computing power comparable to a data center server rack, or even an entire server.

Silicon Photonics Integration: TSMC is developing Compact Universal Photonic Engine (COUPE ) technology to support the explosive growth in data transmission that comes with the AI boom. COUPE uses SoIC-X chip stacking technology to stack an electrical die on top of a photonic die, offering the lowest impedance at the die-to-die interface and higher energy efficiency than conventional stacking methods.

TSMC plans to qualify COUPE for small form factor pluggables in 2025, followed by integration into CoWoS packaging as co-packaged optics (CPO) in 2026, bringing optical connections directly into the package.

Automotive Advanced Packaging: After introducing the N3AE “Auto Early” process in 2023, TSMC continues to serve our automotive customers’ needs for greater computing power that meets the safety and quality demands of the highway by integrating advanced silicon with advanced packaging.

TSMC is developing InFO-oS and CoWoS-R solutions for applications such as advanced driver assistance systems (ADAS), vehicle control, and vehicle central computers, targeting AEC-Q100 Grade 2 qualification by fourth quarter of 2025.

(Photo credit: TSMC)

SK hynix announced today that it recorded 12.43 trillion won in revenues, 2.886 trillion won in operating profit (with an operating margin of 23%), and 1.917 trillion won in net profit (with a net margin of 15%) in the first quarter.

With revenues marking an all-time high for a first quarter and the operating profit a second-highest following the records of the first quarter of 2018, SK hynix believes that it has entered the phase of a clear rebound following a prolonged downturn.

The company said that an increase in the sales of AI server products backed by its leadership in AI memory technology including HBM and continued efforts to prioritize profitability led to a 734% on-quarter jump in the operating profit. With the sales ratio of eSSD, a premium product, on the rise and the average selling prices rising, the NAND business has also achieved a meaningful turnaround in the same period.

SK hynix forecasts the overall memory market to be on a steady growth path in coming months as demand for AI memory continues to rise, while the market for the conventional DRAM also starts to recover from the second half. Industry experts believe that inventories both at suppliers and customers will decrease as an increase in production of premium products such as HBM requires higher production capacities than conventional DRAM, resulting in a relative reduction in conventional DRAM supply.

(Photo credit: SK Hynix)

SK Hynix announced on April 24th that it plans to expand production capacity of the next-generation DRAM including HBM, a core component of the AI infrastructure, in response to the rapidly increasing demand for AI semiconductors.

As the board of directors approves the plan, SK Hynix will build the M15X fab in Cheongju, North Chungcheong Province, for a new DRAM production base, and invest about 5.3 trillion won for fab construction.

SK Hynix plans to start construction at the end of April with an aim to complete in November 2025 for an early mass production. With a gradual increase in equipment investment planned, the total investment in building the new production base will be more than 20 trillion won in the long-term.

With the advent of the AI era, the semiconductor industry believes that the DRAM market has entered a mid- to long-term growth phase. Along with HBM, which is expected to grow more than 60% annually, SK Hynix forecasts that demand for general DRAM will be on a steady rise led by high-capacity DDR5 module products for servers.

As HBM requires at least twice as large capabilities to secure the same production as general DRAM products, SK Hynix decided that increasing DRAM capabilities with a focus on HBM is a precondition for future growth.

The company plans to produce new DRAM from the M15X in Cheongju before the completion of the first fab in Yongin Semiconductor Cluster in the first half of 2027. Being located near the M15, which has been expanding TSV capabilities, the M15X is the best conditioned for optimization of HBM production.

Separately, SK Hynix will proceed with other domestic investments including the Yongin Semiconductor Cluster, where it will to inject approximately 120 trillion won, as planned.

The Yongin project is gaining speed with the process rate for groundwork marking 26%, which is 3% faster than the target. Major preparatory works including land compensation procedures and investigation of cultural properties have been completed, and construction of the infrastructure ranging from power and water to roads is also gaining speed. The company plans to start construction of the first fab in Yongin in March next year and complete it in May 2027.

(Photo credit: SK Hynix)

According to the latest memory spot price trends released by TrendForce, overall DRAM spot market demand has not further heated up, and transaction volume has further shrunk. NAND Flash, affected by pessimistic demand, is experiencing a lack of enthusiasm in market price inquiry transactions. For more details:

DRAM Spot Market:

In the spot market, demand has not risen further for chips, and the overall transaction volume continues to shrink. Most module houses have been slow to reduce inventory, so the situation with spot trading has not been ideal. However, procurement momentum is relatively healthy for server DRAM RDIMMs mainly because DRAM suppliers have significantly increased contract prices for these products, thereby causing some increase in demand in the spot market.

Overall, various DRAM products are currently not consistent in terms of price increases and declines. Further observations on the demand situations across different application segments are necessary to determine their price trends. The average spot price of mainstream chips (i.e., DDR4 1Gx8 2666MT/s) rose by 0.21% from US$1.945 last week to US$1.949 this week.

NAND Flash Spot Market:

Price inquiries have not been robust under a poor outlook on demand as the spot market has started manifesting room for negotiations with channel traders, or even module houses, experiencing an excessive inventory, alongside the obstruction on a further hike of 3D wafer prices. Spot prices of 512Gb TLC wafers have dropped by 0.03% this week, arriving at US$3.764.