According to a report from Korean media outlet viva100, Samsung has signed a new USD 3 billion agreement with processor giant AMD to supply HBM3e 12-layer DRAM for use in the Instinct MI350 series AI chips. Reportedly, Samsung has also agreed to purchase AMD GPUs in exchange for HBM products, although details regarding the specific products and quantities involved remain unclear.

Earlier market reports indicated that AMD plans to launch the Instinct MI350 series in the second half of the year as an upgraded version of the Instinct MI300 series. The MI350 series is reportedly expected to adopt TSMC’s 4-nanometer process, delivering improved computational performance with lower power consumption. The inclusion of 12-layer stacked HBM3e memory will enhance both bandwidth and capacity.

In October 2023, at Samsung Memory Tech Day 2023, Samsung announced the launch of a new HBM3e codenamed “Shinebolt.” In February of this year, Samsung unveiled the industry’s first HBM3e 12H DRAM, featuring 12 layers and a capacity of 36GB, marking the highest bandwidth and capacity HBM product to date. Samsung has provided samples and plans to commence mass production in the second half of the year.

Samsung’s HBM3e 12H DRAM offers up to 1280GB/s bandwidth and 36GB capacity, representing a 50% increase compared to the previous generation of eight-layer stacked memory. Advanced Thermal Compression Non-Conductive Film (TC NCF) technology enables the 12-layer stack to meet HBM packaging requirements while maintaining chip height consistency with eight-layer chips.

Additionally, optimizing the size of chip bumps improves HBM thermal performance, with smaller bumps located in signal transmission areas and larger bumps in heat dissipation areas, contributing to higher product yields.

The adoption of HBM3e 12-layer DRAM over HBM3e 8-layer DRAM has shown an average speed improvement of 34% in AI applications, with inference service users increasing by over 11.5 times.

In view of this matter, industry sources cited by the report from TechNews has indicated that this deal is separate from negotiations between AMD and Samsung Foundry for wafer production. AMD plans to assign a portion of new CPUs/GPUs to Samsung for manufacturing, which is unrelated to this specific transaction.

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• [News] Samsung Reportedly Establishes New HBM Team, Looking to Improve AI Chip Yield
• [News] Memory Manufacturers Vie for HBM3e Market

(Photo credit: Samsung)

To enhance the supply chain capabilities in Europe and strengthen outsourced backend manufacturing operations in the region, major automotive and power semiconductor manufacturer Infineon announced an expanded partnership with semiconductor packaging and testing services provider Amkor Techology. According to the official press release of Infineon, the two companies will establish a new packaging and testing center in Porto, Portugal, with operations expected to commence in the first half of 2025.

Through this agreement, Infineon and Amkor will further strengthen their partnership and expand the semiconductor assembly and testing business model while enhancing the resilience of the European semiconductor supply chain.

Amkor’s facility in Porto, Portugal specializes in semiconductor packaging, assembly, and testing. As part of the reported expansion, cleanroom production lines will be established. Infineon is expected to provide product design and development expertise, as Infineon already operates a large service center in Porto with over 600 employees.

Infineon noted that the establishment of this production center will allow for further expansion of business in Portugal and reinforce the importance of Europe as a semiconductor manufacturing base. This initiative is anticipated to enhance regional manufacturing flexibility and supply security for customers.

On another front, Infineon recently announced a memorandum of understanding with HD Korea Shipbuilding & Offshore Engineering (HD KSOE), a company dedicated to developing environmentally friendly and low-carbon shipping technologies using electricity and hydrogen power. Together, they will leverage power semiconductor technology to jointly develop emerging marine engines and electrification of mechanical systems, accelerating the realization of low-carbon shipping.

In this collaboration, Infineon will provide technical support and guidance to HD KSOE in terms of power semiconductor modules and system solutions. Infineon will also share information on semiconductor trends relevant to maritime applications. The goal of HD KSOE is to enhance the reliability and performance of ship propulsion and drive technologies through this partnership, promoting environmental sustainability through maritime electrification initiatives.

(Photo credit: Infineon)

The US-China tech conflict has extended to RISC-V chips. Reuters reported on April 24th that the US Department of Commerce, in a letter dated around April 15th to members of Congress, highlighted concerns regarding China’s involvement in open-source RISC-V chip technology.

The Department of Commerce is reportedly assessing the potential national security risks associated with this and evaluating whether appropriate actions within its authority can effectively address any concerns.

According to the same report, the US Department of Commerce has emphasized in its letter the need for caution to avoid harming US companies participating in international organizations related to RISC-V technology. Previously, measures shifting control of 5G technology to China have posed obstacles for US companies in international standard-setting bodies (where China is also involved), thereby threatening America’s leadership position in the field.

RISC-V is an open-source architecture independent of the ARM architecture controlled by the UK-based semiconductor design company Arm, as well as the x86 architecture developed by the US chip giant Intel. RISC-V is utilized in various products, including smartphone chips and advanced processors for AI, making it a crucial component in the industry.

In an effort to break through US technology restrictions, China is reportedly placing significant emphasis on RISC-V technology. This has turned RISC-V into a new battleground in the US-China technology conflict.

As early as October 2023, Chairman Michael McCaul of the House Foreign Affairs Committee pointed out that China is abusing RISC-V to circumvent America’s dominant position in intellectual property required for chip design. McCaul cautioned against supporting China’s technology transfer strategy, as it would weaken US export control laws.

Regarding China’s promotion of RISC-V technology, Republican Senator Marco Rubio has warned that if the US does not expand export controls to address this threat, China could one day surpass the US and become the global leader in chip design.

Rubio’s statement underscores concerns within the US government about the strategic implications of China’s efforts to advance its semiconductor capabilities using technologies like RISC-V. The potential for China to gain a competitive edge in this critical sector is viewed as a significant national security issue by some US policymakers.

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• [News] Arm’s Former CEO Engages in RISV-V Market
• [News] U.S. Department of Commerce Claims Huawei Chips Not as Advanced, Lag Behind U.S. Chips by Several Years

(Photo credit: iStock)

TSMC today unveiled its newest semiconductor process, advanced packaging, and 3D IC technologies for powering the next generation of AI innovations with silicon leadership at the Company’s 2024 North America Technology Symposium.

TSMC debuted the TSMC A16TM technology, featuring leading nanosheet transistors with innovative backside power rail solution for production in 2026, bringing greatly improved logic density and performance. TSMC also introduced its System-on-Wafer (TSMC-SoW™) technology, an innovative solution to bring revolutionary performance to the wafer level in addressing the future AI requirements for hyperscaler datacenters.

“We are entering an AI-empowered world, where artificial intelligence not only runs in data centers, but PCs, mobile devices, automobiles, and even the Internet of Things,” said TSMC CEO Dr. C.C. Wei. “At TSMC, we are offering our customers the most comprehensive set of technologies to realize their visions for AI, from the world’s most advanced silicon, to the broadest portfolio of advanced packaging and 3D IC platforms, to specialty technologies that integrate the digital world with the real world.”

New technologies introduced at the symposium include:

TSMC A16TM Technology: With TSMC’s industry-leading N3E technology now in production, and N2 on track for production in the second half of 2025, TSMC debuted A16, the next technology on its roadmap.

A16 will combine TSMC’s Super Power Rail architecture with its nanosheet transistors for planned production in 2026. It improves logic density and performance by dedicating front-side routing resources to signals, making A16 ideal for HPC products with complex signal routes and dense power delivery networks.

Compared to TSMC’s N2P process, A16 will provide 8-10% speed improvement at the same Vdd (positive power supply voltage), 15- 20% power reduction at the same speed, and up to 1.10X chip density improvement for data center products.

TSMC NanoFlexTM Innovation for Nanosheet Transistors: TSMC’s upcoming N2 technology will come with TSMC NanoFlex, the company’s next breakthrough in design-technology co optimization. TSMC NanoFlex provides designers with flexibility in N2 standard cells, the basic building blocks of chip design, with short cells emphasizing small area and greater power efficiency, and tall cells maximizing performance. Customers are able to optimize the combination of short and tall cells within the same design block, tuning their designs to reach the optimal power, performance, and area tradeoffs for their application.

N4C Technology: Bringing TSMC’s advanced techynology to a broader range of of applications, TSMC announced N4C, an extension of N4P technology with up to 8.5% die cost reduction and low adoption effort, scheduled for volume production in 2025.

N4C offers area-efficient foundation IP and design rules that are fully compatible with the widely-adopted N4P, with better yield from die size reduction, providing a cost-effective option for value-tier products to migrate to the next advanced technology node from TSMC.

CoWoS, SoIC, and System-on-Wafer (SoW): TSMC’s Chip on Wafer on Substrate (CoWoS) has been a key enabler for the AI revolution by allowing customers to pack more processor cores and high-bandwidth memory (HBM) stacks side by side on one interposer. At the same time, our System on Integrated Chips (SoIC) has established itself as the leading solution for 3D chip stacking, and customers are increasingly pairing CoWoS with SoIC and other components for the ultimate system-in-package (SiP) integration.

With System-on-Wafer, TSMC is providing a revolutionary new option to enable a large array of dies on a 300mm wafer, offering more compute power while occupying far less data center space and boosting performance per watt by orders of magnitude.

TSMC’s first SoW offering, a logic only wafer based on Integrated Fan-Out (InFO) technology, is already in production. A chip-on-wafer version leveraging CoWoS technology is scheduled to be ready in 2027, enabling integration of SoIC, HBM and other components to create a powerful wafer-level system with computing power comparable to a data center server rack, or even an entire server.

Silicon Photonics Integration: TSMC is developing Compact Universal Photonic Engine (COUPE ) technology to support the explosive growth in data transmission that comes with the AI boom. COUPE uses SoIC-X chip stacking technology to stack an electrical die on top of a photonic die, offering the lowest impedance at the die-to-die interface and higher energy efficiency than conventional stacking methods.

TSMC plans to qualify COUPE for small form factor pluggables in 2025, followed by integration into CoWoS packaging as co-packaged optics (CPO) in 2026, bringing optical connections directly into the package.

Automotive Advanced Packaging: After introducing the N3AE “Auto Early” process in 2023, TSMC continues to serve our automotive customers’ needs for greater computing power that meets the safety and quality demands of the highway by integrating advanced silicon with advanced packaging.

TSMC is developing InFO-oS and CoWoS-R solutions for applications such as advanced driver assistance systems (ADAS), vehicle control, and vehicle central computers, targeting AEC-Q100 Grade 2 qualification by fourth quarter of 2025.

(Photo credit: TSMC)

SK hynix announced today that it recorded 12.43 trillion won in revenues, 2.886 trillion won in operating profit (with an operating margin of 23%), and 1.917 trillion won in net profit (with a net margin of 15%) in the first quarter.

With revenues marking an all-time high for a first quarter and the operating profit a second-highest following the records of the first quarter of 2018, SK hynix believes that it has entered the phase of a clear rebound following a prolonged downturn.

The company said that an increase in the sales of AI server products backed by its leadership in AI memory technology including HBM and continued efforts to prioritize profitability led to a 734% on-quarter jump in the operating profit. With the sales ratio of eSSD, a premium product, on the rise and the average selling prices rising, the NAND business has also achieved a meaningful turnaround in the same period.

SK hynix forecasts the overall memory market to be on a steady growth path in coming months as demand for AI memory continues to rise, while the market for the conventional DRAM also starts to recover from the second half. Industry experts believe that inventories both at suppliers and customers will decrease as an increase in production of premium products such as HBM requires higher production capacities than conventional DRAM, resulting in a relative reduction in conventional DRAM supply.

(Photo credit: SK Hynix)