The discovery of TSMC-manufactured chips in Huawei devices has sparked significant concern among U.S. lawmakers. John Moolenaar, Chairman of the U.S. Congressional Committee on the Chinese Communist Party (CCP) and a Republican Congressman, criticized the reports, calling it a “catastrophic failure” of U.S. export control policies. He urged both the U.S. Commerce Department and TSMC to promptly explain the affected parties and the scale of the incident.

In his statement, Moolenaar said, “Reports that cutting-edge TSMC-manufactured chips have contributed to Huawei’s AI development represent a catastrophic failure of U.S. export control policy. AI accelerators, like the one these chips powered, are at the forefront of our technological competition with the CCP, and I fear the damage here will have significant consequences for national security. Congress needs immediate answers from both BIS and TSMC regarding the scope and volume of this disaster. The U.S. government must take immediate steps to ensure this does not happen again.”

The controversy revolves around a Huawei chip produced by TSMC. Last week, a report by The Information revealed that the U.S. Commerce Department is investigating whether TSMC has been involved in manufacturing AI chips designed by Huawei, which have become popular with Chinese customers as alternatives to NVIDIA chips, now restricted due to U.S. export regulations.

Following the Information report, a teardown of Huawei’s Ascend 910B AI chip revealed that it was manufactured by TSMC using its 7-nanometer process. In response, Reuters reported on the 22nd that TSMC had notified Washington about a possible attempt by Huawei to bypass U.S. export controls.

TSMC reportedly informed the U.S. Commerce Department after receiving an order for a chip similar to Huawei’s Ascend 910B, a processor designed for training large language models, according to Financial Times. How this chip ended up in Huawei’s possession remains unclear.

Before U.S. sanctions were imposed, TSMC had produced an earlier version of the 910B chip, Financial Times notes.

In addition, Liberty Times reported, citing industry insiders, that a Chinese design company suspected of acting as a proxy for Huawei submitted an order to TSMC earlier this year for a 7-nanometer project, paying several hundred million dollars in full for wafer production.

(Photo credit: TSMC)

According to a recent press release from the U.S. Department of Commerce, the department has partnered with optical semiconductor company Infinera under the CHIPS Act, signing a non-binding memorandum of understanding to provide up to USD 93 million in funding.

This subsidy will support Infinera in building a new 3,700-square-meter wafer manufacturing facility in San Jose, California, which will increase the company’s production capacity of indium phosphide (InP) photonic integrated circuits (PICs) tenfold. Additionally, Infinera will establish a testing and advanced packaging center in Bethlehem, Pennsylvania, expanding production capabilities for 2.5D/3D packaging and co-packaged optics (CPO).

Infinera also plans to apply for an investment tax credit from the U.S. Department of the Treasury. The combined incentives from the federal government are expected to exceed USD 200 million.

Infinera is a vertically integrated U.S. semiconductor manufacturer with over 20 years of experience, specializing in producing photonic chips (PICs) using indium phosphide (InP) technology. Infinera’s photonic chips enable efficient data transmission for broadband networks, data centers, and AI-driven applications by integrating multiple optical functions onto a single chip. These circuits reduce power consumption and operational costs while optimizing network performance.

Industry reports from June 2023 revealed that Nokia announced plans to acquire Infinera for USD 2.3 billion, with the transaction expected to close in the first half of 2025. This acquisition will expand Nokia’s market access in North America and better support Infinera’s customers outside the region.

Highly Anticipated Photonic Chips

Currently, optical modules primarily follow two integration schemes: one based on indium phosphide (InP) and another on silicon photonics (SiPh). Additionally, a future technology, thin-film lithium niobate (TFLN), is on the horizon. Leading companies in this field include Infinera, Acacia, Inphi, Ciena, and Huawei. Acacia and Inphi are well-known silicon photonics integration chip manufacturers, while Infinera focuses on indium phosphide.

In the silicon photonics space, since 1985, the technology has undergone significant evolution. Initially, the focus was on developing high-confinement waveguide technology. Over time, silicon photonics has not only achieved strategic integration with the CMOS industry in terms of materials, integration, and packaging but has also established its dominance in the transceiver market.

On the other hand, the most prominent use of indium phosphide (InP) is in optoelectronics. InP lasers generate light for optical communication systems worldwide, ranging from fiber connections and networks to free-space optical communications.

After decades of development, researchers are now focused on building mature photonic integrated circuits on InP substrates. Applications have expanded from communication technologies to sensors and imaging systems in the automotive, medical, and other markets.

In the modern AI era, data centers have become the primary and most direct application scenario for both InP and silicon photonics integration schemes. Indium phosphide (InP) allows for monolithic integration of active components (lasers, amplifiers) but is limited by smaller wafer sizes. Silicon photonics, on the other hand, leverages the mature large-scale silicon wafer CMOS manufacturing process but requires heterogenous integration of active components.

Over the past decade, numerous PIC technologies for data center interconnects have been developed and commercialized, with transmission rates expanding from 40G to 800G.

(Photo credit: Infinera)

According to SEMI, the global shipments of silicon wafers are projected to decline 2% to 12,174 million square inches (MSI) in 2024, while strong rebound of 10% is expected in 2025, with shipments projected to reach 13,328 MSI as demand continues to recover.

The report suggests that strong silicon wafer shipment growth is anticipated to continue through 2027.

Increasing demand related to AI and advanced processing is expected to drive improved fab utilization rate for global semiconductor production capacity, according to SEMI.

In addition, the growing demand for silicon wafers is also driven by new applications in advanced packaging and the production of high-bandwidth memory (HBM), as indicated by SEMI.

According to the forecast report from SEMI, global silicon wafer shipments will reach 14,507 MSI in 2026. In 2027, it is expected to reach 15,413 MSI, surpassing the highest record of 14,565 in 2022.

(Photo credit: Intel)

Kioxia is set to introduce its progress on DRAM storage-class memory (SCM) and 3D-NAND technologies at the IEEE International Electron Devices Meeting (IEDM) 2024 conference in San Francisco in December, featuring its Oxide-Semiconductor Channel Transistor DRAM (OCTRAM) technology jointly developed with Taiwan memory chipmaker Nanya Technology, as well as MRAM-based storage-class memory jointly developed with SK hynix, according to a report from Block and Files.

Kioxia will reportedly present a new type of DRAM with oxide semiconductors that reduce power consumption, MRAM suitable for larger capacities for SCM applications, and a new 3D NAND structure with superior bit density and performance.

According to the report, Kioxia has developed the DRAM with oxide semiconductors with Nanya Technology. This Oxide-Semiconductor Channel Transistor DRAM (OCTRAM) features a gate-all-round InGaZnO (Indium Gallium Zinc Oxide) vertical transistor with the oxide that can reduce current leakage to an “extremely low” level. According to Kioxia’s press release, the technology has the potential to reduce power consumption across various applications, such as AI, post-5G communication systems, and IoT devices.

The MRAM-based storage-class memory is developed with SK hynix. According to Kioxia’s press release, the companies have achieved cell read/write operation at the smallest-ever scale of cell half-pitch of 20.5 nanometers for MRAM. The press release pointed out that memory reliability tends to degrade as cells are miniaturized. The companies develop a new read/write method that can reduce the unwanted capacitance that occurs in the readout circuits.  According to Kioxia’s press release, this technology has practical applications for AI and big data processing.

Last, Kioxia developed a new 3D NAND structure, aiming to enhance reliability and prevent the performance degradation of NAND-type cell. In conventional structures, degradation of performance typically occurs when the number of stacked layers increases. Compared to the conventional structure that stacks NAND-type cells vertically, the new structure arranges NAND-type cells horizontally. The press release indicated that this new structure makes it possible to develop 3D flash memory with high bit density and reliability at low cost.

(Photo credit: Kioxia)

Following Qualcomm’s recent launch of Snapdragon 8 Elite, it was confronted by Arm Holdings to terminate its architectural license agreement with Qualcomm, which permitted the U.S. chip giant to use Arm’s intellectual property for chip design, according to Bloomberg. According to the reports by MoneyDJ and Commercial Times, Taiwan-based smartphone IC designer MediaTek may turn out to be the main beneficiary amid the dispute.

According to media reports, Arm has issued a mandatory 60-day notice to Qualcomm regarding the cancellation of the licensing agreement, which previously enabled the latter to develop its own chips based on Arm’s proprietary standards.

Citing sources familiar with the industry, the report by MoneyDJ notes that the move implies the strained relationship between a major IP supplier and a leading mobile chip firm. If the licensing agreement does break up, it would be detrimental to both parties. Therefore, Arm’s act seems rather to be a “push for peace through conflict,” the source observes.

According to sources cited by the Commercial Times, it is likely that the two parties would eventually reach a reconciliation, as Arm’s ultimate goal might be securing a share of the profits from the Snapdragon series chips. While the AI PC ecosystem led by Arm architecture is still in its nascent stage, the company can only garner more licensing fees if Qualcomm actively promotes its WoA (Windows on Arm) products, the report suggests.

According to Commercial Times, MediaTek will likely benefit as brand manufacturers prefer chip suppliers with no litigation concerns and who also offer competitive pricing.

MediaTek’s upcoming launch of a Windows on Arm (WoA) solution will further strengthen its collaboration between Arm and Taiwanese manufacturers, the report notes. A previous report by Wccftech notes that MediaTek has teamed up with NVIDIA to develop a custom chip to confront Qualcomm’s Snapdragon X Elite series, which will be manufactured using TSMC’s 3nm node, based on ARM architecture.

On the other hand, institutional investors cited by MoneyDJ also believe that the ongoing lawsuit between Arm and Qualcomm could benefit MediaTek, helping the Taiwanese chip giant further expand its market share in the flagship smartphone segment. It is also worth noting that MediaTek’s newly-launched Dimensity 9400 reportedly offers higher price-performance ratio compared to Qualcomm’s Snapdragon 8 Elite, according to MoneyDJ.

According to a report by Wccftech, MediaTek’s Dimensity 9400, built with TSMC’s N3E node, may be priced at around USD 155 per chipset, reportedly 20% higher than that of the Dimensity 9300. Also built with TSMC’s N3E node, Qualcomm’s Snapdragon 8 Elite is expected to be priced at around USD 180, with an ASP increase of about 15%, according to analyst Ming-Chi Kuo.

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• [News] Arm Holdings Reportedly Cancels Qualcomm Chip Design License
  
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(Photo credit: MediaTek)