The semiconductor industry enters the era of integration. Various foundries are focusing on advanced packaging technologies, but the terminology surrounding advanced packaging can be daunting. This article aims to explain these terms in the simplest way possible.

According to a report from TechNews, currently, there are two main trends in advanced packaging: heterogeneous integration and chiplets.

In fact, the concept of “heterogeneous integration” has been developing for many years and is not exclusive to advanced packaging. It is not only used for the integration of heterogeneous chiplets but also for integrating other non-chip active/passive components into a single package, which is the technology commonly used in traditional Outsourced Semiconductor Assembly and Test Services(OSATs).

• Heterogeneous Integration = Big Building Blocks? Advanced Packaging = Small Building Blocks? 

In the simplest terms, “heterogeneous integration” can be likened to building with large building blocks, while “advanced packaging” is akin to assembling with small building blocks. Some manufacturers, like traditional Outsourced Semiconductor Assembly and Test Services(OSATs), excel in stacking large blocks, such as logic circuits, radio frequency circuits, MEMS (Micro-Electro-Mechanical Systems), or sensors, onto a IC substrate. The stacking of these different large blocks represents the concept of heterogeneous integration.

On the other hand, some blocks are too small to stack effectively, requiring assistance from advanced packaging, typically provided by semiconductor foundries.

Advanced packaging also encompasses 2.5D packaging and 3D packaging. Using the metaphor of building blocks, the former involves horizontally stacking small building blocks on a interposer, while the latter involves vertically stacking small building blocks with interconnection facilitated through Through-Silicon Vias (TSVs), which are ultra-small building blocks.

It’s important to emphasize that stacking blocks is a conceptual representation, and the distinction between large and small blocks is relative. The analogy above refers to heterogeneous integration in traditional packaging, and heterogeneous integration in advanced packaging follows a similar concept, but with even smaller building blocks.

• SoC / SiP / Heterogeneous Integration / Chiplet

With this concept in mind, let’s discuss the applications of heterogeneous integration in advanced packaging:

Among the various packaging types, SoC (System On Chip) involves integrating different chips such as processors and memory, with different functions, redesigned and fabricated using the “same process,” integrated onto a single chip, resulting in a final product with only one chip.

On the other hand, SiP (System in Package) involves connecting multiple chips with “different processes” through “heterogeneous integration” technology, integrated within the same packaging module. Therefore, the final product will be a system with many chips on it, resembling the stacking of different-sized building blocks mentioned earlier.

Therefore, heterogeneous integration refers to integrating different and separately manufactured components (heterogeneous) into higher-level assemblies. These components include blocks of different sizes, such as MEMS devices, passive components, logic chips, and more.

However, at a certain point, for the sake of process development, researchers found that separating components at the right time might facilitate miniaturization. Hence, chiplet was born.

• Is Chiplet the Fusion of Heterogeneous Integration and Advanced Processes?

As demands for ICs become increasingly complex, the size of SoC chips continues to grow. However, cramming too many components onto a limited substrate poses significant challenges, including heightened process complexity and reduced yield.

Hence, the concept of chiplets emerged, advocating for the segmentation of SoC functionalities, such as data storage, computation, signal processing, and data flow management, into smaller individual chips. These chiplets are then integrated through packaging to form a interconnected network.

It’s worth noting that Chiplets are essentially chips, whereas SiP refers to the packaging format. Chiplet architecture enable the reduction of individual chip sizes, simplify circuit design, overcome manufacturing difficulties and yield issues, and offer greater design flexibility.

• Advanced Packaging Technologies in Foundries

Currently, advanced packaging can be broadly categorized into three main types: Wafer-Level Packaging (WLP), 2.5D Packaging, and 3D Packaging. Traditional packaging involves cutting wafers into chips before packaging, while advanced packaging entails packaging the silicon wafer before cutting, requiring subsequent stacking processes in fabs. Therefore, the technology is primarily the responsibility of fabs.

Traditional packaging involves cutting wafers into chips before packaging. Advanced packaging, starting from wafer-level packaging, involves packaging silicon wafers before cutting, and subsequent stacking requires wafer fabrication processes.

Therefore, this article will delve into advanced packaging technologies offered by the three major foundries, with a focus on 2.5D and 3D packaging.

• 2.5DIC / 3DIC Packaging

To further explain using building blocks, the difference between 2.5D and 3DIC packaging lies in the “stacking method.”

In 2.5D packaging, processors, memory, or other chips are stacked horizontally on a silicon interposer using a flip-chip method, with micro bumps connecting different chip’s electronic signals. Through silicon vias (TSVs) in the interposer link to the metal bumps below, then packaged onto the IC substrate, creating tighter interconnections between the chips and the substrate.

In a side view, although the chips are stacked, the essence remains horizontal packaging, with the chips positioned closer together and allowing for smaller chip sizes. Additionally, this is a form of “heterogeneous integration” technology.

3D packaging involves stacking multiple chips (face down) together, directly using through-silicon vias to stack them vertically, linking the electronic signals of different chips above and below, achieving true vertical packaging. Currently, more and more CPUs, GPUs, and memories are starting to adopt 3D packaging technology.

• Hybrid Bonding

Hybrid bonding is one of the die bonding techniques used in advanced chip packaging processes. One of the commercially available technologies in this domain is the “Cu-Cu hybrid bonding.”

In traditional wafer bonding processes, there are interfaces between copper and dielectric materials. With “Cu-Cu hybrid bonding,” metal contacts are embedded within the dielectric material. Through a thermal treatment process, these two materials are bonded together, utilizing the atomic diffusion of copper metal in its solid-state to achieve the bond. This approach addresses challenges encountered in previous flip-chip bonding process.

Compared to flip-chip bonding, hybrid bonding offers several advantages. It allows for achieving ultra-high I/O counts and longer interconnect lengths. By using dielectric material for bonding instead of bottom fillers, the cost of filling is eliminated.

Additionally, hybrid bonding results in minimal thickness compared to chip-on-wafer bonding. This is particularly beneficial for future developments in 3D packaging, where stacking multiple layers of chips is required, as hybrid bonding can significantly reduce the overall thickness.

• Advanced Packaging Moves Towards the Era of Heterogeneous Integration

As the semiconductor industry enters the “post-Moore’s Law era,” the development focus of advanced packaging is gradually shifting from 2D planar structures to 3D stacking and from single-chip designs to multi-chip configurations. Therefore, “heterogeneous integration” will play a crucial role in future advanced packaging.

Currently, prominent companies such as TSMC, Samsung, and Intel are intensifying their research and development efforts and capacity expansions in this field, introducing their innovative packaging solutions.

With ongoing technological advancements and innovations, advanced packaging and heterogeneous integration will play increasingly vital roles in propelling the semiconductor industry towards greater heights, meeting the complex and diverse demands of future electronic devices.

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• [News] The Era of Heterogeneous Integration Approaches: Who Shall Dominate the Advanced Packaging Field?

(Photo credit: Intel)

In 2022, Intel engaged in negotiations with the Italian government, planning to invest USD 5 billion in constructing a packaging and testing facility. This project would also receive subsidies from the Italian government, expected to cover 40% of the construction costs, along with additional subsidies or incentives. Furthermore, Intel intended to establish a research and design center in France, expected to create a complete semiconductor supply chain in Europe.

However, according to a report from Reuters, Italian Minister of Industry Adolfo Urso has indicated that Intel may delay or abandon its investment plans in Italy and France to fulfill its prior commitments in Germany. Nonetheless, Italy has not completely given up on attracting Intel; Adolfo Urso emphasizes that Italy remains very welcoming if Intel changes its mind.

On the other hand, according to another previous report from Reuters, the US government is expected to announce a significant grant for Intel’s Arizona project soon. This grant will be part of the USD 39 billion direct appropriations and USD 75 billion loans and guarantees under the “Chip Act.”

Among the recipients of subsidies under the “Chip Act,” Intel is expected to receive the largest subsidy to date. According to a previous report from Tom’s Hardware, Intel is anticipated to receive a government subsidy of USD 10 billion, with TSMC and Samsung potentially included in the latest subsidy list as well.

Samsung Electronics is, according to its own expectation, investing USD 17 billion to construct a foundry in Taylor, Texas, while TSMC is investing roughly USD 40 billion to build a foundry in Phoenix, Arizona. However, there are rumors suggesting that due to the U.S. prioritizing domestic companies, the expected subsidy amounts for Intel may differ from those for TSMC and Samsung.

The U.S. government enacted the “Chip Act” in 2022, but subsidies have been modest, with only three American companies currently benefiting, including BAE Systems, GlobalFoundries, and Microchip Technology.

In order to accelerate the development of the IDM 2.0 initiative, Intel made a significant expansion decision in 2021, investing approximately USD 20 billion in the Octillo campus in Arizona, USA. This investment involved the construction of two new fabs and the implementation of EUV production lines to support Intel’s 20A and Intel’s 18A process technologies. The new Fab 52 and Fab 62 are expected to commence operations in 2024.

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• [News] Intel Submits Conceptual Drawings for Fab Construction in Germany, Installing High-NA EUV Exposure Machines
• [News] GlobalFoundries Reportedly Becomes Third Recipient of CHIPS Act Subsidy, Receives USD 1.5 Billion

(Photo credit: Intel)

Chip giant NVIDIA kicked off its annual Graphics Processing Unit (GPU) Technology Conference (GTC) today, with CEO Jensen Huang announcing the launch of the new artificial intelligence chip, Blackwell B200.

According to a report from TechNews, this new architecture, Blackwell, boasts a massive GPU volume, crafted using TSMC’s 4-nanometer (4NP) process technology, integrating two independently manufactured dies, totaling 208 billion transistors. These dies are then bound together like a zipper through the NVLink 5.0 interface.

NVIDIA utilizes a 10 TB/sec NVLink 5.0 to connect the two dies, officially termed NV-HBI interface. The NVLink 5.0 interface of the Blackwell complex provides 1.8 TB/sec bandwidth, doubling the speed of the NVLink 4.0 interface on the previous generation Hopper architecture GPU.

As per a report from Tom’s Hardware, the AI computing performance of a single B200 GPU can reach 20 petaflops, whereas the previous generation H100 offered a maximum of only 4 petaflops of AI computing performance. The B200 will also be paired with 192GB of HBM3e memory, providing up to 8 TB/s of bandwidth.

NVIDIA’s HBM supplier, South Korean chipmaker SK Hynix, also issued a press release today announcing the commencement of mass production of its high-performance DRAM new product, HBM3e, with shipments set to begin at the end of March.

Source: SK Hynix

Recently, global tech companies have been heavily investing in AI, leading to increasing demands for AI chip performance. SK Hynix points out that HBM3e is the optimal product to meet these demands. As memory operations for AI are extremely fast, efficient heat dissipation is crucial. HBM3e incorporates the latest Advanced MR-MUF technology for heat dissipation control, resulting in a 10% improvement in cooling performance compared to the previous generation.

Per SK Hynix’s press release, Sungsoo Ryu, the head of HBM Business at SK Hynix, said that mass production of HBM3e has completed the company’s lineup of industry-leading AI memory products.

“With the success story of the HBM business and the strong partnership with customers that it has built for years, SK hynix will cement its position as the total AI memory provider,” he stated.

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• [News] Foxconn Capitalizes on AI Opportunities? Reportedly Looking at Apple’s AI Server Market, B200 Also Poised to Succeed
• [News] NVIDIA and AMD Clash in AI Chip Market, as TSMC Dominates Orders with Strong Momentum in Advanced Processes

(Photo credit: NVIDIA)

Benefited from robust demand in downstream application markets, the silicon carbide (SiC) industry is in high gear. According to TrendForce, the SiC power device market is expected to reach USD 5.33 billion by 2026, with its mainstream applications still highly reliant on electric vehicles and renewable energy sources.

Recently, the widely-publicized SiC market has seen new developments involving companies such as Mitsubishi Electric, Mersen, and Ascen Power.

• Mitsubishi Electric to Begin Construction of SiC Fab in April

According to recent reports from Nikkei, Mitsubishi Electric plans to commence construction of a new 8-inch SiC fab in Kumamoto Prefecture, Japan, in April 2024, with operations scheduled to start in April 2026.

In March 2023, Mitsubishi Electric announced the plan to invest approximately JPY 100 billion (Around CNY 4.856 billion) over five years to construct an 8-inch SiC fab and enhance related production facilities. The fab is projected to kick-start operation in April 2026.

The new fab, spanning six floors with a total floor area of around 42,000 square meters, will primarily handle front-end processes for 8-inch SiC wafers. Mitsubishi Electric will introduce an automated transport system across all processes to create a highly efficient production line and plans to gradually increase capacity, aiming to increase SiC production capacity by five times by the fiscal year 2026 (compared to fiscal year 2022).

In May 2023, Mitsubishi Electric signed a MOU with Coherent to supply 8-inch n-type 4HSiC wafers for the new factory. Both parties are committed to expanding the production scale of 8-inch SiC devices.

• Ascen Power Accelerates Phase One Capacity Ramp-up of SiC Chip Manufacturing Project

Recently, Shao Yonghua, the plant manager of Ascen Power’s fab, introduced that the entire fab is currently ramping up capacity, with the planned capacity of producing 240,000 pieces of 6-inch automotive-grade SiC chips annually expected to be achieved by the end of this year.

The reserved 8-inch production line is adjacent to the 6-inch line and will have the capability to produce 240,000 pieces of 8-inch automotive-grade SiC chips annually once completed.

As previously reported, Ascen Power’s SiC chip manufacturing project is a major project under Guangdong’s “Strengthening Chip Technology Project,” with a total investment of CNY 7.5 billion, covering an area of 150 acres.

The first phase involves an investment of CNY 3.5 billion to build a production line capable of producing 240,000 pieces of 6-inch SiC chips annually, with the second phase focusing on establishing a production line capable of producing 240,000 pieces of 8-inch SiC chips annually. The products include IGBTs, SiC SBD/JBS, SiC MOSFETs, targeting applications including new energy vehicles, photovoltaics, smart grids.

In November 2022, the project’s clean room was officially put into use, achieving a monthly production capacity of 10,000 pieces. Its automotive-grade and industrial-grade chips have been successfully mass-produced and sampled, and these chips are about to complete the automotive verification. Up to now, Ascen Power has signed agreements with more than 40 customers and achieved tape-out, covering most SiC chip design companies nationwide.

• Mersen To Rev up SiC Wafer Production

On March 12, European graphite materials and silicon carbide wafer supplier Mersen announced that it has received investment from the French government for capacity expansion of its SiC wafer project. The subsidy amount may exceed Euro 12 million (Approximately CNY 94 million), sourced from the “France 2023 Plan”—a significant joint interest project in microelectronics and communication technology in Europe.

Mersen stated that they intend to advance the research and industrial production of p-SiC wafers with this investment. p-SiC is a low-resistivity polycrystalline SiC wafer that can be combined with single-crystal SiC active layers, enabling SiC device manufacturers to improve production yield and transistor performance.

Mersen expects to invest Euro 85 million (Approximately CNY 670 million) between 2023 and 2025, employ 80 to 100 staff, promote capacity construction at the Gennevilliers plant in France, and accomplish a potential manufacturing capacity of 400,000 wafers (150mm) by 2027.

Additionally, Mersen will supply SiC wafers to Soitec. In November 2021, two sides entered into a strategic partnership to jointly develop polycrystalline SiC wafers with extremely low resistivity for SiC power electronic components based on Soitec SmartSiC technology, leveraging their respective expertise in substrates and materials.

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• [News] Continuous Breakthroughs in SiC Substrates, Global 8-Inch Fab to Reach 11

(Photo credit: Mitsubishi Electric)

According to sources cited by Reuters,  TSMC is reportedly considering plans to establish a production line for its CoWoS technology in Japan. However, TSMC has yet to make any further decisions, and they have declined to comment on the matter.

CoWoS is an advanced packaging technology that stacks chips to enhance computing power, reduce energy consumption, and save space. Currently, TSMC’s CoWoS production capacity is entirely located in Taiwan.

With the booming development of artificial intelligence, global demand for advanced semiconductor packaging has surged, prompting chip suppliers like TSMC, Samsung, and Intel to strengthen their advanced packaging capabilities.

Previously, TSMC’s CEO, C.C. Wei, stated that the company plans to double its CoWoS output by the end of 2024 and further increase it in 2025. With TSMC recently completing the first phase of construction for its Kumamoto fab in Japan and announcing plans for the second phase, which will involve collaboration with Japanese companies SONY Semiconductor Solutions and Toyota Motor Corporation, with a total investment exceeding USD 20 billion and utilizing 6/7-nanometer advanced processes.

However, Joanne Chiao, an analyst at market research firm TrendForce, suggests that if TSMC establishes advanced packaging capacity in Japan, it may face limitations in scale. It remains unclear how much demand there is in Japan for CoWoS packaging, but most of TSMC’s CoWoS customers are currently in the United States.

Additionally, sources cited by Reuters’ report indicate that TSMC’s competitor, Intel, is also considering establishing an advanced packaging research facility in Japan to deepen ties with local chip supply chain companies.

Meanwhile, Samsung, another competitor of TSMC, is setting up advanced packaging research facilities in Yokohama, Japan, with government support. Furthermore, Samsung is in discussions with Japanese and other companies regarding material procurement, preparing to launch its packaging technology similar to that used by SK Hynix.

Regarding the development of the semiconductor industry in Japan, as mentioned in a previous report from TrendForce, Japan’s resurgence in the semiconductor arena is palpable, with the Ministry of Economy, Trade, and Industry fostering multi-faceted collaborations with the private sector. With a favorable exchange rate policy aiding factory construction and investments, the future looks bright for exports.

However, the looming shortage of semiconductor talent in Japan is a concern. In response, there are generous subsidy programs for talent development. Japan is strategically positioning itself to reclaim its former glory in the world of semiconductors.

Read more

• [News] Subsidies to TSMC from Japan and China Increase Over Fivefold Annually
• [News] High Efficiency in TSMC Kumamoto Plant Construction Sets Stage for Potential Advanced Packaging Investment in Japan

(Photo credit: TSMC)