According to ChinaTimes’ report, Intel’s strides in European chip manufacturing are narrowing the gap with TSMC.

The Fab 34 in Ireland has taken a significant step in production using EUV for the first time, with Intel 4 technology equivalent to the original 7nm. The research firm IC Knowledge has once assessed that Intel 4 is ahead of TSMC’s 5nm process, emphasizing energy efficiency, which makes it more suitable for mobile devices.

Industry sources note that the upcoming Meteor Lake CPU will adopt the Intel 4 process, and Intel 3 is planned for release by the end of the year. With Intel’s Ireland facility entering mass production, it significantly reduces the gap with TSMC.

Meteor Lake is poised to become the first processor utilizing Intel 4 fabrication technology, marking a milestone as the inaugural process to support EUV lithography exposure.

While the Compute tile is manufactured using Intel 4, the Graphic tile, SoC tile, and IO tile are completed using TSMC’s 5/6nm process. Industry source suggests that TSMC still maintains superior yield rates and more advantageous production costs.

Intel is establishing an advanced semiconductor manufacturing value chain in Europe. Fab 34 in Leixlip, Ireland, is operational, and there are plans to build a fab in Magdeburg, Germany, and an assembly testing facility in Wroclaw, Poland. This positions Intel ahead of TSMC in global layout.

Intel aims to regain a leading position in process technology by 2025, and will receive the industry’s first set of High-NA EUV lithography exposure equipment by the end of the year. The “Intel 3” will kick off vigorously. As Moore’s Law reaches its limits, TSMC, as a frontrunner, will face a gradually narrowing gap with competitors.

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(Photo credit: Intel)

The labor dispute sparked by TSMC’s venture into the United States is poised to come to a close. TSMC’s Arizona plant and the local labor union, Arizona Building and Construction Trades Council (AZBTC), announced an agreement yesterday. TSMC will collaborate with the local union to establish a workforce training program and maintain transparency on public safety issues.

However, TSMC also retains some flexibility, aiming to recruit local employees while seeking the option to hire foreign workers with “specialized experience” if deemed necessary.

It is anticipated that this agreement aligns with TSMC’s prior request for the dispatch of 500 professional equipment engineers from Taiwan to the United States. This move, with the successful acquisition of technical construction permits, is expected to facilitate the expedited installation of equipment, ensuring smooth operational processes in the future.

While TSMC’s move to set up a factory in the United States was fueled by favorable policies, it faced challenges as contractors were unfamiliar with U.S. regulations, causing delays in mechanical and electrical integration and cleanroom construction.

To expedite the installation of advanced process equipment for the groundbreaking four-nanometer fabrication process in the U.S., TSMC had to mobilize nearly 500 personnel from Taiwan for intensive installation work before system integration.

This decision sparked a strong backlash from the AZBTC, criticizing TSMC for disrespecting local technicians’ expertise and raising concerns about TSMC’s potential intention to introduce cheaper labor, impacting local job rights.

Although TSMC consistently emphasized maintaining good interactions with various unions in Arizona, some union representatives were displeased with TSMC’s practice of dispatching personnel through suppliers. Reportedly, they called on the state and federal governments to pressure TSMC, leading to unexpected delays in the installation of new equipment.

After months of negotiation between TSMC and AZBTC, an agreement was reached, listing agreed-upon priority areas, including union training, communication channels, and on-site personnel allocation. However, TSMC, considering global talent distribution, retained the flexibility to hire foreign construction personnel with specific expertise in certain circumstances.

According to the Greater Phoenix Economic Council(GPEC), the specific terms of the agreement reached between the two parties are as follows:

1. Enhanced Workforce Training and Development

A highly skilled, diverse, and inclusive construction workforce is necessary to meet the timelines of the two fabs. The AZBTC intends to recruit a sufficient number of skilled workers to fulfill manpower requirements of TSMC Arizona’s contractors for the Project. TSMC Arizona will partner with AZBTC on the development of union workforce training programs and curricula. The goal will be to build a construction workforce that can support TSMC Arizona in the near and long term with employment opportunities.。

2. Shared Commitment to Site Safety

TSMC Arizona is deeply committed to workplace safety in the operation of all its facilities. To enhance the partnership, TSMC Arizona will maintain transparency with AZBTC with regards to safety assessments, audits, incident records and improvement plans.

3. Industry Leading, Global Workforce

TSMC Arizona is focused on hiring workers locally in the United States. The AZBTC workforce is highly skilled in constructing microchip manufacturing plants. Circumstances may require TSMC Arizona or its vendors to employ foreign workers with specialized experience.

4. Open and Regular Communication

To ensure TSMC Arizona and AZBTC are fulfilling the spirit of the agreement outlined, and accountable to commitments made, ongoing communication and review via regular forums will be critical. A committee will be formed, consisting of members designated by the affiliated AZBTC unions and members designated by TSMC Arizona and the contractors. These meetings will be held quarterly, one of which will be an annual forecast meeting to project future workforce requirements.

The report notes that TSMC also mentioned in a joint statement that its construction of a fab in Arizona represents the largest single foreign direct investment in the state’s history. This wafer fab is set to be the most advanced semiconductor manufacturing base in the United States, creating thousands of stable and high-paying job opportunities locally.

The ongoing construction of the wafer fab’s two-phase project has already generated thousands of jobs in accordance with the prevailing industry wage standards for members of the AZBTC.

(Photo credit: TSMC)

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On the 7th, TSMC convened the 2023 Supply Chain Management Forum, C.C. Wei, President of TSMC, acknowledging persistent inflationary pressures, remains optimistic about 2024. He also cited the rapid growth of AI applications as a key driver of opportunities, reported by CTEE.

Wei addressed the pivotal role of semiconductors in AI development. Looking ahead, the focus extends to continual AI technology advancement and computational power enhancement, with a parallel emphasis on energy consumption reduction. Given projections of AI computational demand tripling in the next 2 years, addressing energy efficiency becomes paramount.

To meet escalating AI computational needs, Wei highlighted the imperative to develop technologies balancing high performance with effective power control. TSMC commits to providing ample production capacity to meet end-user demands while sustaining cost-efficiency.

Global supply chain resilience amid challenges from society, economy, and geopolitics. Collaborating with partners. TSMC navigates 3nm, advanced and specialty processes for capacity expansions, R&D for 2nm and beyond, and global production plans. The company aims to lead through cutting-edge technology and top-notch manufacturing services, fostering innovation for customers.

Apart from the insightful speech, Wei also presented the 2023 Excellent Performance Award during the forum. It recognized suppliers’ performance in technology collaboration, global production support, green manufacturing, fab construction management, production capacity, quality control and other categories. Companies like Applied Materials, ASM International, KLA, Lam Research, TOKYO ELECTRON LIMITED and others.

(Image: TSMC)

Bloomberg reported in early December 2023 that the Chinese government has been directly investing to assist Huawei in building its chip supply chain since 2019, indicating that the ongoing uncertainties in the U.S.-China trade war, the pursuit of semiconductor industry self-sufficiency is expected to be a long-term development direction for China.

TrendForce’s insight:

1. Chinese Government Establishes Investment Fund for Huawei, Creating Exclusive Supply Chain

On May 15, 2019, when the United States announced the inclusion of Huawei and its 70 subsidiaries in the trade blacklist, the Chinese government swiftly established a fund named “Shenzhen Major Industry Investment Group” in Shenzhen, where Huawei’s headquarter is located.

This fund, directly funded by the local government, aimed primarily at creating a large supply chain for Huawei, consisting of optical factories, chip equipment developers, and chemical manufacturers.

One chip manufacturer, SiCarrier, maintained close ties with Huawei. Besides talent exchanges, the company also transferred over a dozen patented technologies to Huawei.

2. Escalating U.S.-China Trade War Drives Long-Term Semiconductor Self-Reliance in China

Recently, the Nikkei news, in collaboration with the research company Fomalhaut Techno Solutions, conducted a renewed disassembly of Huawei’s Mate 60 Pro smartphone. The findings indicate that, based on component costs, approximately 47% of the components are manufactured in China.

This contradicts the earlier claim by Chinese media of a 90% domestic production rate. Nevertheless, the Mate 60 Pro shows a noteworthy 18% increase in domestic production compared to the Mate 40 Pro in 2020.

Additionally, during the component analysis, it was reaffirmed that the self-developed 5G processor, Kirin 9000S, featured in Huawei’s Mate 60 Pro smartphone, has a circuit width of 7nm. This demonstrates China’s semiconductor technological prowess despite restrictions imposed by the U.S. ban.

However, when the semiconductor industry value chain is divided regionally, it can be observed that in the uppermost stream of the supply chain, including electronic design automation software and licensed intellectual property used in chip design, this domain is primarily concentrated in the hands of U.S. firms.

Currently, China’s overall share in the global semiconductor value chain remains relatively low and is more concentrated in downstream packaging and manufacturing. If China aims to establish a fully “self-sufficient” semiconductor supply chain, it is estimated that there is still a long way to go.

However, what is certain is that in the ongoing U.S.-China trade war, the pursuit of semiconductor industry autonomy will be a long-term development direction for China.

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Market reports suggest Nvidia’s new product release cycle has shortened from two to a year, sparking intense competition among major memory companies in the realm of next-gen High Bandwidth Memory (HBM) technology. Samsung, SK Hynix, and Micron are fervently competing, with SK Hynix currently holding the dominant position in the HBM market. However, Micron and Samsung are strategically positioned, poised for a potential overtake, reported by TechNews.

Current Status of the HBM Industry

SK Hynix made a breakthrough in 2013 by successfully developing and mass-producing HBM using the Through Silicon Via (TSV) architecture. In 2019, they achieved success with HBM2E, maintaining the overwhelming advantage in the HBM market. According to the latest research from TrendForce, Nvidia plan to partner with more HBM suppliers. Samsung, as one of the suppliers, its HBM3 (24GB) is anticipated to complete verification with NVIDIA by December this year.

Regarding HBM3e progress, Micron, SK Hynix, and Samsung provided 8-layer (24GB) Nvidia samples in July, August, and October, respectively, with the fastest verification expected by year-end. All three major players anticipate completing verification in the first quarter of 2024.

As for HBM4, the earliest launch is expected in 2026, with a stack increase to 16 layers from the existing 12 layers. The memory stack will likely adopt a 2048-bit memory stack connection interface, driving demand for the new “Hybrid Bonding” stacking method. The 12-layer HBM4 product is set to launch in 2026, followed by the 16-layer product expected in 2027.

Navigating HBM4, the New Technologies and Roadmaps of Memory Industry Leaders

SK Hynix

According to reports from Business Korea, SK Hynix is preparing to adopt “2.5D Fan-Out” packaging for the next-generation HBM technology. This move aims to enhance performance and reduce packaging costs. This technology, not previously used in the memory industry but common in advanced semiconductor manufacturing, is seen as having the potential to “completely change the semiconductor and foundry industry.” SK Hynix plans to unveil research results using this packaging method as early as next year.

The 2.5D Fan-Out packaging technique involves arranging two DRAM horizontally and assembling them similar to regular chips. The absence of a substrate beneath the chips allows for thinner chips, significantly reducing the thickness when installed in IT equipment. Simultaneously, this technique bypasses the Through Silicon Via (TSV) process, providing more Input/Output (I/O) options and lowering costs. 

According to their previous plan, SK Hynix aims to mass-produce the sixth-generation HBM (HBM4) as early as 2026. The company is also actively researching “Hybrid Bonding” technology, likely to be applied to HBM4 products.

Currently, HBM stacks are placed on the interposer next to or GPUs and are connected to their interposer. While SK Hynix’s new goal is to eliminate the interposer completely, placing HBM4 directly on GPUs from companies like Nvidia and AMD, with TSMC as the preferred foundry.

Samsung

Samsung is researching the application of photonics in HBM technology’s interposer layer, aiming to address challenges related to heat and transistor density. Yan Li, Principal Engineer in Samsung’s advanced packaging team, shared insights at the OCP Global Summit in October 2023.

(Image: Samsung)

According to Samsung, The industry has made significant strides in integrating photonics with HBM through two main approaches. One involves placing a photonics interposer between the bottom packaging layer and the top layer containing GPU and HBM, acting as a communication layer. However, this method is costly, requiring an interposer and photon I/O for logic chips and HBM.

(Image: Samsung)

The alternative approach separates the HBM memory module from packaging, directly connecting it to the processor using photonics. Rather than dealing with the complexity of packaging, a more efficient approach is to separate the HBM memory module from the chip itself and connect it to the logic IC using photonics technology. This approach not only simplifies the manufacturing and packaging costs for HBM and logic ICs but also eliminates the need for internal digital-to-optical conversions in the circuitry. However, careful attention is required to address heat dissipation.

Micron

As reported by Tom’s Hardware, Micron’s 8-layer HBM3e (24GB) is expected to launch in early 2024, contributing to improved AI training and inference performance. The 12-layer HBM3e (36GB) chip is expected to debut in 2025.

Micron is working on HBM4 and HBM4e along with other companies. The required bandwidth is expected to exceed 1.5 TB/s. Micron anticipates launching 12-layer and 16-layer HBM4 with capacities of 36GB to 48GB between 2026 and 2027. After 2028, HBM4E will be introduced, pushing the maximum bandwidth beyond 2+ TB/s and increasing stack capacity to 48GB to 64GB.

Micron is taking a different approach from Samsung and SK Hynix by not integrating HBM and logic chips into a single die, suggested by Chinese media Semiconductor Industry Observation. This difference in strategy may lead to distinct technical paths, and Micron might advise Nvidia, Intel, AMD that relying solely on the same company’s chip carries greater risks.

(Image: Micron)

TSMC Aids Memory Stacking       

Currently, TSMC 3DFabric Alliance closely collaborates with major memory partners, including Micron, Samsung, and SK Hynix. This collaboration ensures the rapid growth of HBM3 and HBM3e, as well as the packaging of 12-layer HBM3/HBM3e, by providing more memory capacity to promote the development of generative AI.

(Image: TSMC)

(Image: SK Hynix)

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