According to TechNews, Taiwan’s semiconductor foundry, PSMC (Powerchip Semiconductor Manufacturing Corporation) recently announced its collaboration with Tata Electronics in India to establish the country’s first 12-inch wafer fabrication plant in Dholera, Gujarat. In an interview on the 4th, Chairman Frank Huang stated that Powerchip’s role primarily involves technology transfer, rather than financial investment, with Tata Group’s wafer plant expected to break ground on March 12.

Huang disclosed that the initiative is 70% funded by the Indian government, which had actively sought Taiwanese semiconductor firms to assist in India. This partnership with India will see PSMC aiding in the plant’s construction, while the operational responsibilities will wholly fall under India’s purview.

Following the agreement between the two parties on February 6, the groundbreaking ceremony, to be presided over by the President of India, is scheduled for this month on the 12th, with Huang himself attending.

Furthermore, Huang mentioned three major projects by the Indian government, including the collaboration between PSMC and Tata, support for Micron Technology’s manufacturing presence in India, and a back-end packaging initiative. Through PSMC’s assistance, the Tata Group plans to produce power management ICs, display drivers, microcontrollers, and high-performance computing logic chips at the 12-inch wafer facility, targeting automotive, computing and data storage, wireless communication, and artificial intelligence application markets.

(Image: PSMC)

In recent years, with the continuous surge in demand for Silicon Carbide (SiC) substrates, the call for cost reduction in SiC has been growing stronger, as the ultimate product price remains the key determinant for consumers. The cost of SiC substrates accounts for the highest proportion in the entire cost structure, reaching around 50%.

This means that cost reduction and utilization rate improvement in the substrate segment are particularly crucial. Therefore, large-size substrates, due to their cost advantages, are gradually being placed with high expectations.

According to the calculation by Chinese SiC substrate manufacturer TankeBlue Semiconductor, upgrading from 4 inches to 6 inches is expected to reduce costs by 50% per unit; from 6 inches to 8 inches, costs are expected to decrease by an additional 35% on top of that.

Meanwhile, 8-inch substrates can yield more chips, resulting in lower edge wastage. In simple terms, 8-inch substrates offer higher utilization rate, which is the main reason why major manufacturers are actively developing them.

Currently, 6-inch SiC substrates are still dominant, but 8-inch substrates are beginning to penetrate the market. For instance, in July 2023, Wolfspeed announced that its 8-inch fab had begun shipping SiC MOSFETs to Chinese customers, indicating its bulk shipment of 8-inch SiC substrates. TankeBlue Semiconductor has also started small-scale shipments of 8-inch substrates, with plans to achieve medium-scale shipments by 2024.

Accelerated Advancement of 8-Inch SiC Substrate Lineup

Since Wolfspeed first showcased samples in 2015, the 8-inch SiC substrate has undergone a development history of 7-8 years, with significant acceleration in technology and product development in the past two years.

Looking at international manufacturers, aside from Wolfspeed, which has achieved mass production, there are seven SiC substrate, epitaxial, expected to achieve mass production of 8-inch substrates this year or in the next 1-2 years.

In terms of investment, Wolfspeed continues to construct the John Palmour Silicon Carbide Manufacturing Center (SiC substrate facility) in North Carolina, USA. This facility will further drive the expansion of substrate production capacity to meet the increasing demand for 8-inch wafers.

Coherent also announced plans last year to expand its production of 8-inch substrates and epitaxial wafers, with large-scale expansion projects in the United States and Sweden. In terms of product export channels, Coherent has received a USD 1 billion investment from Mitsubishi Electric and Denso to provide long-term 6/8-inch SiC substrates and epitaxial wafers to both companies.

STMicroelectronics also invested in the 8-inch domain last year by partnering with Hunan Sanan Semiconductor to construct an 8-inch SiC fab. The latter will accompany it by establishing an 8-inch SiC substrate plant, ensuring stable material supply for the joint venture. Simultaneously, ST is developing its own substrates and previously collaborated with Soitec to achieve mass production of 8-inch SiC substrates.

Turning to Chinese manufacturers, currently, over 10 enterprises have entered the sampling and small-scale production stages for 8-inch SiC substrates. These include companies such as Semisic Crystal Co., Jingsheng Mechanical & Electrical Co., SICC Co., Summit Crystal Semiconductor Co., Synlight Semiconductor Co., TanKeBlue Semiconductor Co., Harbin KY Semiconductor, IV Semitec, Sanan Semiconductor, Hypersics, and Yuehaijin Semiconductor Materials Co.

In addition to the mentioned companies, there are many other Chinese manufacturers currently researching 8-inch substrates, such as GlobalWafers, Dongni Electronics, Hesheng Silicon Industry, Tiancheng Semiconductor.

At present, the gap between Chinese substrate manufacturers and international giants has narrowed significantly. Companies like Infineon have established long-term partnerships with Chinese manufacturers such as SICC Co. and TanKeBlue Semiconductor Co.. From a technological standpoint, this narrowing gap reflects the overall improvement in substrate technology globally. Moving forward, concerted efforts from various manufacturers are expected to drive the development of 8-inch substrate technology.

Overall, there is a growing momentum in the overall development of 8-inch SiC substrates, with significant breakthroughs in both quantity and quality.

Global 8-Inch SiC Fabs Accelerate Expansion

As substrate materials continue to break through technological ceilings, the expansion scale of global 8-inch SiC fabs reached new heights in 2023.

As per TrendForce, approximately 12 expansion projects related to 8-inch wafers were implemented in 2023. Among them, 8 projects were led by global manufacturers such as Wolfspeed, Onsemi, STMicroelectronics, Infineon, Rohm, and others. STMicroelectronics also collaborated with Sanan Semiconductor on one project. Additionally, 3 projects were spearheaded by Chinese manufacturers such as Global Power Technology, United Nova Technology Co., and J2 Semiconductor.

From a regional perspective, significant investments in new 8-inch SiC fabs are expected in key regions such as Europe, America, Japan, South Korea, China, and Southeast Asia. As of now, there are approximately 11 8-inch fabs either under construction or planned globally (with clearer details).

These include 2 facilities by Wolfspeed (in Mohawk, USA, and Saarland, Germany), 1 by Bosch (in Roseville, USA), 1 self-built by STMicroelectronics (in Catania, Italy), 1 joint venture with Sanan (in Chongqing, China), 1 by Infineon (in Kulim, Malaysia), 1 by Mitsubishi Electric (in Kumamoto, Japan), 2 by Rohm (in Chikugo, Japan, and Kunitomi, Japan), 1 by ON Semiconductor (in Bucheon, South Korea), and 1 by Fuji Electric (in Matsumoto, Japan).

Regarding the expansion directions of manufacturers, Bosch and ON Semiconductor’s investments in 2023 are directly aimed at the automotive SiC market. STMicroelectronics’s planned 8-inch SiC chip factory in Italy also targets the electric vehicle market. While other manufacturers have not explicitly stated the application direction of future production capacity, electric vehicles are the primary growth engine for SiC both currently and in the future, making it a focal point for expansion among major manufacturers.

In the electric vehicle sector, the 800V high-voltage platform has emerged as a clear development trend. The 800V platform requires higher-voltage power semiconductor components, prompting manufacturers to begin developing 1200V SiC power devices.

From a cost perspective, although 6-inch wafers are currently mainstream in the short term, the trend towards larger sizes like 8-inch is inevitable for cost reduction and efficiency improvement purposes. Therefore, the electric vehicle market is expected to drive continuous growth in demand for 8-inch wafers in the future.

From a supply chain perspective, transitioning to 8-inch wafers represents a breakthrough for SiC manufacturers. Per industry insights, the 6-inch SiC device market has entered a phase of intense competition, particularly in the SiC JBD. For smaller-scale and less competitive enterprises, profit margins are increasingly squeezed, indicating an impending round of consolidation and restructuring in the future.

Read more

• [In-Depth Analyses] China Advances to 8-Inch SiC Substrates in 2023

In June 2023, leading processor manufacturer Intel reached an agreement with the German federal government, announcing the signing of an amended investment memorandum. The plan involves investing over EUR 30 billion to construct two new fabs in Magdeburg. The German federal government has agreed to provide a subsidy of EUR 10 billion, including incentives and subsidies from the European Chips Act and government initiatives.

According to a report by Tom’s Hardware citing sources, Intel has submitted conceptual drawings for a new fab in Germany. The initial plans include two fabs, designated as Fab 29.1 and Fab 29.2, equipped with the world’s most advanced semiconductor tools.

Moreover, Intel reportedly has ample space for up to six additional fabs. The first batch of two fabs is expected to commence operations in the fourth quarter of 2027, with both the Intel 14A (1.4nm) and Intel 10A (1nm) advanced processes believed to be part of the plan.

As per previous reports from TechNews, Intel has not disclosed any details regarding the 10A node, but it promises at least double-digit improvements in power consumption and performance. Intel CEO Pat Gelsinger has previously stated that new processes typically improve critical dimensions by approximately 14% to 15%. Therefore, it is plausible that the 10A and 14A nodes will also experience similar improvements.

Source: Intel

As per Intel’s roadmap, Intel 14A is also optimized in 2027, so it seems that 10A falls between 14A and 14A-E.

The report from Tom’s Hardware further indicates that Fab 29.1 and Fab 29.2, the two three-story buildings, occupy approximately 81,000 square meters, with a total length of 530 meters and a width of 153 meters. Each floor has a height ranging from 5.7 to 6.5 meters. Including the roof structure for air conditioning and heating, the building reaches a height of 36.7 meters.

The High-NA EUV exposure machines are installed on the second floor with a height of 6.5 meters, while the upper and lower floors are used for material logistics, providing necessary resources such as water, electricity, and chemicals.

ASML models that the 1st generation of the High-NA-enabled production node will employ between 4 to 9 High-NA EUV exposures and a total of 20 to 30 EUV exposures, encompassing both Low-NA and High-NA.

Read more

• [News] Advancing into Intel 10A! Intel’s 2027 Blueprint Adds 1-Nanometer Process
• [News] Intel Promotes 1.8-Nanometer Process in South Korea, Reportedly Pledges Various Benefits to Startups

(Photo credit: Intel)

NVIDIA has yet to officially announce the exact release dates for its next-generation AI chip architectures, the Blackwell GPU, and the B100 chip. However, Dell’s Chief Operating Officer, Jeff Clarke, recently revealed ahead of schedule during Dell’s Q4 2024 Earnings Call that NVIDIA is set to introduce the Blackwell architecture next year, with plans to release not only the B100 chip but also another variant, the B200 chip.

Following Dell’s recent financial report, Clarke disclosed in a press release that NVIDIA is set to unveil the B200 product featuring the Blackwell architecture in 2025.

Clarke also mentioned that Dell’s flagship product, the PowerEdge XE9680 rack server, utilizes NVIDIA GPUs, making it the fastest solution in the company’s history. He expressed anticipation for NVIDIA’s release of the B100 and B200 chips. This news has sparked significant market interest, as NVIDIA has yet to publicly mention the B200 chip.

Clarke further stated that the B200 chip will showcase Dell’s engineering expertise in high-end servers, especially in liquid cooling systems. As for the progress of the B100 chip, NVIDIA has yet to disclose its specific parameters and release date.

NVIDIA’s current flagship H200 chip in the high-performance computing market adopts the Hopper GPU architecture paired with HBM3e memory chips, considered the most capable chip for AI computing in the industry.

However, NVIDIA continues to accelerate the development of its next-generation AI chip architectures. According to NVIDIA’s previously disclosed development roadmap, the next-generation product after the H200 chip is the B100 chip. Therefore, the expectation was that the B100 chip would be the highest-specification chip based on the Blackwell GPU architecture. Nevertheless, with the emergence of the B200 chip, it has sparked further speculation.

Previously, media speculation cited by the report from Commercial Times stated based on the scale of the H200 chip that the computational power of the B100 chip would be at least twice that of the H200 and four times that of the H100.

Read more

• [News] NVIDIA Expands Advanced Packaging Supply Chain with Intel’s Inclusion, Diverting Orders from TSMC
• [News] NVIDIA Reportedly Overwhelms TSMC with 3 and 4-Nanometer Orders

(Photo credit: NVIDIA)

The annual AI event, NVIDIA GTC (GPU Technology Conference), is set to take place on March 17th, as H200 and the next-generation B100 will reportedly be announced ahead of schedule to seize the market. According to Commercial Times’ report citing sources, H200 and the upcoming B100 will adopt TSMC’s 4-nanometer and 3-nanometer processes respectively. H200 is expected to be launched in the second quarter, while it’s rumored that orders for the B100 adopting Chiplet architecture have already been placed for production.

Sources cited by the report also indicate that NVIDIA’s orders are robust, pushing TSMC’s 3 and 4-nanometer production capacity to near full utilization, making the first quarter, traditionally a slow season, unexpectedly busy.

Regarding the matter of NVIDIA’s next-generation chip orders overwhelming TSMC’s advanced processes, TSMC stated that details regarding production capacity remain consistent with the previous earnings call and will not be elaborated further.

Still, Commercial Times further cited industry sources, revealing that TSMC, in response to anticipated capacity constraints by 2023, is accelerating its efforts. Particularly focusing on advanced packaging like CoWoS, they’ve not only relocated equipment from the Longtan facility but also swiftly activated the AP6 plant in Zhunan.

Another industry sources reportedly indicate that the planned construction of the Tongluo
facility, initially slated for the second half of this year, is now scheduled to commence in the second quarter. The aim is to ramp up 3D Fabric capacity to produce 110,000 12-inch wafers per month by the first half of 2027.

Meanwhile, TSMC’s advanced processes remain fully utilized, with capacity utilization exceeding 90% in February, driven by sustained AI demand.

NVIDIA, on the other hand, recently emphasized that computational-intensive tasks like Generative AI and large language models require multiple GPUs. From customer purchase to model deployment, it takes several quarters. Thus, this year’s inference applications stem from GPU purchases made last year. As model parameters grow, GPU demand is expected to expand.

In addition to increasing GPU quantities, NVIDIA’s GPU efficiency is poised for a significant boost this year. The Blackwell series, notably the B100, is hailed as NVIDIA’s next-generation GPU powerhouse by the market.

Not only is it the first to adopt TSMC’s 3-nanometer process, but it’s also the pioneer in Chiplet and CoWoS-L packaging among NVIDIA products. This tackles high power consumption and cooling issues, with projected single-card efficiency and transistor density expected to surpass AMD’s MI300 series set to debut in the first quarter.

Read more

• [News] NVIDIA Expands Advanced Packaging Supply Chain with Intel’s Inclusion, Diverting Orders from TSMC
• [News] NVIDIA CEO Jensen Huang Meets with TSMC Executives in Taiwan, Addressing the Significant AI Chip Shortage

(Photo credit: Kioxia)