Microsoft announced the in-house AI chip, Azure Maia 100, at the Ignite developer conference in Seattle on November 15, 2023. This chip is designed to handle OpenAI models, Bing, GitHub Copilot, ChatGPT, and other AI services. Support for Copilot, Azure OpenAI is expected to commence in early 2024.

TrendForce’s Insights:

1. Speculating on the Emphasis of Maia 100 on Inference, Microsoft’s Robust Ecosystem Advantage is Poised to Emerge Gradually

Microsoft has not disclosed detailed specifications for Azure Maia 100. Currently, it is known that the chip will be manufactured using TSMC’s 5nm process, featuring 105 billion transistors and supporting at least INT8 and INT4 precision formats. While Microsoft has indicated that the chip will be used for both training and inference, the computational formats it supports suggest a focus on inference applications.

This emphasis is driven by its incorporation of the less common INT4 low-precision computational format in comparison to other CSP manufacturers’ AI ASICs. Additionally, the lower precision contributes to reduced power consumption, shortening inference times, enhancing efficiency. However, the drawback lies in the sacrifice of accuracy.

Microsoft initiated its in-house AI chip project, “Athena,” in 2019. Developed in collaboration with OpenAI. Azure Maia 100, like other CSP manufacturers, aims to reduce costs and decrease dependency on NVIDIA. Despite Microsoft entering the field of proprietary AI chips later than its primary competitors, its formidable ecosystem is expected to gradually demonstrate a competitive advantage in this regard.

2. U.S. CSP Manufacturers Unveil In-House AI Chips, Meta Exclusively Adopts RISC-V Architecture

Google led the way with its first in-house AI chip, TPU v1, introduced as early as 2016, and has since iterated to the fifth generation with TPU v5e. Amazon followed suit in 2018 with Inferentia for inference, introduced Trainium for training in 2020, and launched the second generation, Inferentia2, in 2023, with Trainium2 expected in 2024.

Meta plans to debut its inaugural in-house AI chip, MTIA v1, in 2025. Given the releases from major competitors, Meta has expedited its timeline and is set to unveil the second-generation in-house AI chip, MTIA v2, in 2026.

Unlike other CSP manufacturers, both MTIA v1 and MTIA v2 adopt the RISC-V architecture, while other CSP manufacturers opt for the ARM architecture. RISC-V is a fully open-source architecture, requiring no instruction set licensing fees. The number of instructions (approximately 200) in RISC-V is lower than ARM (approximately 1,000).

This choice allows chips utilizing the RISC-V architecture to achieve lower power consumption. However, the RISC-V ecosystem is currently less mature, resulting in fewer manufacturers adopting it. Nevertheless, with the growing trend in data centers towards energy efficiency, it is anticipated that more companies will start incorporating RISC-V architecture into their in-house AI chips in the future.

3. The Battle of AI Chips Ultimately Relies on Ecosystems, Microsoft Poised for Competitive Edge

The competition among AI chips will ultimately hinge on the competition of ecosystems. Since 2006, NVIDIA has introduced the CUDA architecture, nearly ubiquitous in educational institutions. Thus, almost all AI engineers encounter CUDA during their academic tenure.

In 2017, NVIDIA further solidified its ecosystem by launching the RAPIDS AI acceleration integration solution and the GPU Cloud service platform. Notably, over 70% of NVIDIA’s workforce comprises software engineers, emphasizing its status as a software company. The performance of NVIDIA’s AI chips can be further enhanced through software innovations.

On the contrary, Microsoft possess a robust ecosystem like Windows. The recent Intel Arc GPU A770 showcased a 1.7x performance improvement in AI-driven Stable Diffusion on Microsoft Olive, this demonstrates that, similar to NVIDIA, Microsoft has the capability to enhance GPU performance through software.

Consequently, Microsoft’s in-house AI chips are poised to achieve superior performance in software collaboration compared to other CSP manufacturers, providing Microsoft with a competitive advantage in the AI competition.

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• [News] Microsoft First In-House AI Chip “Maia” Produced by TSMC’s 5nm

Recently, the seven major foundries —TSMC, GlobalFoundries, UMC, SMIC, Hua Hong Semiconductor, VIS, and PSMC—have successively released their third-quarter financial reports and held performance briefings to explain the semiconductor industry’s business climate and the outlook for the next stage.

Overall, in the third quarter, both the revenue and net profit of the seven foundries showed a YoY decline compared to the same period last year. From the perspective of capacity utilization and foundry pricing, except for TSMC benefiting from advanced processes, seeing a rebound in capacity utilization and stable pricing, the other six all experienced declines in both data.

Recent news on foundry pricing and capacity utilization has been continuous. This article will take a closer look at the data of the above seven major foundries and the latest market dynamics to glimpse into the fourth quarter of this year and the trends in foundry services next year.

How did the seven foundries perform in Q3, and what about their capacity utilization?

TSMC

In the third quarter, TSMC’s consolidated revenue was TWD 546.73 billion, approximately USD 1.731 billion, a YoY decrease of 10.8% but a QoQ increase of 13.7%. The net profit for the third quarter was TWD 211 billion, approximately  USD 6.677 billion, a YoY decrease of 25.0%, but a QoQ increase of 16.0%. TSMC expects fourth-quarter sales to be USD 18.8~19.6 billion, with a gross profit margin of 51.5% to 53.5%.

In the first and second quarters of this year, it was said that TSMC’s 7nm capacity utilization rate had dropped to below 50%. However, in the second half of the year, benefiting from Apple expanding its new product lineup and companies like Nvidia and Qualcomm entering the 3nm era in the second half of 2024, the industry estimates that TSMC’s 7/6nm capacity utilization will hold at around 70% by the end of this year, and 5/4nm will be close to 80%, with a monthly production capacity of about 60,000~70,000 wafers by the end of this year.

GlobalFoundries

GlobalFoundries’ Q3 revenue decreased by 11% to $1.85 billion, and the net profit was USD 249 million, lower than the USD 337 million in the same period last year. GlobalFoundries CEO Thomas Caulfield stated in the financial report, “although the global economic and geopolitical landscape remains uncertain, we are collaborating closely with our customers to support their efforts to reduce inventory levels.”

UMC

UMC’s consolidated revenue for Q3 was USD 1.77 billion, a 1.37% increase compared to the second quarter but a 24.3% decrease compared to the third quarter of 2022. The gross profit margin for the third quarter was 35.9%, and the net profit was USD 495 million.

UMC’s utilization showed a significant decline during the second and third quarters, with its capacity utilization dropping from 71% in the second quarter to 67% in the third quarter, according to the company.

Looking ahead, UMC Chairman Jason Wang stated that short-term demand in the computer and communication sectors is gradually picking up in the fourth quarter, and the automotive market remains challenging. Customers continue to manage inventory levels cautiously, and the expected utilization in the fourth quarter is about 61% to 63%, with a QoQ decrease of about 5%, average selling prices remaining stable, and a gross profit margin of about 31% to 33%.

SMIC

SMIC’s Q3 revenue was USD 1.62 billion, a YoY decrease of 15.0% but a QoQ increase of 3.9%. Net profit attributable to shareholders of the parent company was CNY 678 million (approximately USD 95 million), a YoY decrease of 78.41% and a QoQ decrease of 51.81%.

In terms of production capacity, SMIC’s Q3 capacity was approximately 795,750 8-inch equivalent wafers (an increase of 41,500 8-inch equivalent wafers compared to the second quarter’s 754,250 wafers), with a capacity utilization rate of 77.1%.

Looking to the fourth quarter, SMIC expects sales revenue to increase by 1% to 3% QoQ, and the gross profit margin will continue to bear the pressure from new capacity depreciation, expected to be between 16% and 18%.

Hua Hong Semiconductor

Hua Hong’s Q3 revenue was s USD 568.5 million, a YoY decrease of 5.13% and a QoQ decrease of 8.08%. Net profit attributable to parent company was USD 95.83 million, a YoY decrease of 86.36% and a QoQ decrease of 82.40%.

Looking ahead to the fourth quarter of 2023, Hua Hong expects sales revenue to be between USD 450~500 million, with a gross profit margin of about 2% to 5%.

In terms of production capacity, as of the end of the third quarter, Hua Hong Semiconductor’s equivalent 8-inch wafer monthly production capacity increased to 358,000 wafers, with an overall capacity utilization rate of 86.8%.

VIS (Vanguard International Semiconductor)

In the third quarter, VIS’s consolidated revenue was TWD 10.557 billion, approximately USD 334 million, an increase of 7.1% QoQ.

VIS’s outlook is relatively conservative. The company expects the semiconductor supply chain to cautiously control inventory in the fourth quarter. Although the adjustment of consumer electronics inventory is nearing completion, adjustments in the automotive and industrial sectors are later. The company expects a significant adjustment in the fourth quarter, with an estimated QoQ decrease of 8% to 10% in wafer shipments, a QoQ decrease in capacity utilization in the mid-single digits, between 55% and 60%. The average selling price (ASP) of products is estimated to decrease by 2% or less per quarter, and the gross profit margin will continue to decline to between 22% and 24%.

In recent information revealed by the supply chain regarding foundry pricing, VIS might experience a pricing decline of up to 5% in the second half of the year. Big clients may even have the opportunity to negotiate a discount of up to 10%. This trend is expected to continue into the first quarter of next year, with a further reduction, possibly moving from single-digit to double-digit percentages.

PSMC

Q3 financial reports from PSMC show that, impacted by the decline in both capacity utilization and selling prices, the third-quarter main business recorded an expanded loss of TWD 1.408 billion (approximately USD 44.59 million)) and the after-tax net profit turned into a net loss of TWD 334 million(approximately USD 10 million).

PSMC General Manager Brian Shieh revealed that the market conditions in the third quarter still faced headwinds. To maintain competitiveness, PSMC has reduced prices to customers by about 4% to 5%.

It is reported that PSMC’s third-quarter capacity utilization is around 60%, and the gross profit margin is also impacted by idle capacity losses, dropping to 9.2%.

Regarding future demand, Shieh stated that the supply chain has now descended to a reasonable level, with market demand appearing in areas such as mobile driver ICs and surveillance camera CIS components. Visibility is expected to extend to around one quarter, so he is optimistic that PSMC’s fourth-quarter operations will grow by around mid-single digits.

The overall market sentiment is gradually clearing in anticipation of inventory corrections.

In general, as the fourth quarter is coming to an end, most companies still hold conservative views. In the consumer electronics field, such as PCs and smartphones, inventory adjustments have gradually reached the end, and some have already enjoyed the benefits of an upturn. However, inventory adjustments for automotive electronics and industrial applications are expected to lag, and this downturn is expected to be extended.

Among them, the views of TSMC and SMIC are worth noting. TSMC stated that customer inventory digestion will continue into the fourth quarter. Regarding the automotive and industrial platforms and AI businesses that TSMC has recently actively sought to expand, TSMC President C.C. Wei warned that the demand for AI is “not enough to offset” the weakening demand for chips in consumer electronic products on its earnings call in October.

Haijun Zhao, co-CEO of SMIC, stated that in the fields of smartphone and industrial control, Chinese customers have basically reached a balanced inventory level. However, European and American customers are still at historically high levels. Secondly, the relevant inventory of automotive products has begun to be on the high side, causing customers to be alert to market corrections, and orders are quickly tightening. Additionally, there are signs of a recovery in the third quarter in the smartphone terminal market, and the industry. As a whole, he believes that there will be a rebound in overall consumer electronics next year.

Regarding whether the global semiconductor foundry industry is slowly recovering from a downturn, TrendForce pointed out that in 2023, terminal demand is gradually recovering, and AI and automotive demand are maintaining growth momentum. AI servers are expected to grow by more than 37% in the next three years, and electric vehicles with the support of autonomous driving will have a compound annual growth rate of 30% to 40% in the next three years. Smartphones are expected to end their downward trend in 2024, with a growth rate of 2.9%, and servers will have a growth rate of 2.3%, overall leading to an increase in demand for foundry.

On the other hand, 8-inch wafer capacity utilization rate of foundries will gradually rise in 2024. The 8-inch production line produces products such as MOSFET, IGBT, and PMIC will still focus on 12-inch wafers capacity expansion in the next few years. In addition to adopting solutions from existing chip suppliers, the trend of customized chips has also emerged, and high-speed computing applications have become the biggest driving force for advanced processes. TrendForce predicts that the global foundry industry will experience a slight increase in 2024, reaching a growth rate of 6.4%.

According to Bloomberg’ report, TSMC is contemplating the construction of its third wafer fabrication plant in Kumamoto, Japan, focusing on the 3-nanometer manufacturing process. This move could position Japan as a global hub for semiconductor manufacturing.

After being inquired by Taiwan’s media, Economic Daily News, TSMC responded on November 21 to these rumors, stating that the expansion of the company’s global manufacturing footprint is driven by factors such as customer demand, business opportunities, operational efficiency, government support, and economic considerations.

In the response, TSMC also mentioned that it continues to make necessary investments to support customer needs and address the structural growth in semiconductor technology’s long-term demand. Currently, the company is actively evaluating the possibility of establishing a second wafer fabrication plant in Japan, with no additional information available for sharing.

Bloomberg reports that TSMC has informed its supply chain partners about considering the construction of a third plant in Kumamoto, codenamed ” TSMC Fab-23 Phase 3,” but the commencement date remains uncertain.

Analyst Joanne Chiao from TrendForce points out that Japan’s expertise in materials and machinery is one of the factors attracting TSMC’s expansion. Japan stands to benefit from TSMC’s establishment as the pace of creating a local semiconductor ecosystem by Japanese government surpasses that of the U.S. government.

In addition to TSMC, Japan has successfully attracted investments from Micron, Samsung, and Powerchip Semiconductor Manufacturing Corporation (PSMC). Japanese government is also assisting the local Rapidus in constructing a 2-nanometer chip plant in Hokkaido.

TSMC’s current overseas facility receiving the largest subsidy is its first new plant in Kumamoto, Japan. TSMC holds the majority of shares in the Kumamoto plant and collaborates with customers and Japanese officials through joint ventures with Sony Semiconductor Solutions Corporation and DENSO Corporation, investing in the plant’s subsidiary, JASM. The plant is set to enter mass production by the end of 2024, producing chips in 22/28-nanometer and 12/16-nanometer processes.

Due to strong support from Japanese authorities, TSMC’s capital expenditure for its first new plant in Kumamoto has increased from $7 billion to $8.6 billion. The Japanese Ministry of Economy, Trade, and Industry approved a subsidy of JPY 476 billion (approximately USD 3.5 billion) in June of the previous year, translating to 40% of the total capital expenditure of TSMC’s new facility.

Following the confirmation of an expanded subsidy program by Japanese authorities, TSMC is planning to build a second wafer fabrication plant near the first one. Rumors suggest that as early as 2025, TSMC may introduce Extreme Ultraviolet (EUV) lithography machines for production in processes below 7 nanometers.

(Photo credit: TSMC)

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• [News] TSMC’s Kumamoto Plant Prepares for 2024 Mass Production with 1000+ Employees, Followed by Taiwanese Material Suppliers’ Collaboration
• [News] Japanese Gov’t Grants TSMC 900B Yen, Kumamoto Fab 2 Announcement Soon

Intel’s upcoming Lunar Lake platform has entrusted TSMC with the 3nm process of its CPU. This marks TSMC’s debut as the exclusive producer for Intel’s mainstream laptop CPU, including the previously negotiated Lunar Lake GPU and high-speed I/O (PCH) chip collaborations. This move positions TSMC to handle all major chip orders for Intel’s crucial platform next year, reported by UDN News.

Regarding this news, TSMC refrained from commenting on single customer business or market speculations on November 21st. Intel has not issued any statements either.

Recent leaks of Lunar Lake platform internal design details from Intel have generated discussions on various foreign tech websites and among tech experts on X (formerly known as Twitter). According to the leaked information, TSMC will be responsible for producing three key chips for Intel’s Lunar Lake—CPU, GPU, and NPU—all manufactured using the 3nm process. Orders for high-speed I/O chips are expected to leverage TSMC’s 5nm production, with mass production set to kick off in the first half of next year, aligning with the anticipated resurgence of the PC market in the latter half of the year.

While TSMC previously manufactured CPUs for Intel’s Atom platform over a decade ago, it’s crucial to note that the Atom platform was categorized as a series of ultra-low-voltage processors, not Intel’s mainstream laptop platform. In recent years, Intel has gradually outsourced internal chips, beyond CPUs, for mainstream platforms to TSMC, including the GPU and high-speed I/O chips in the earlier Meteor Lake platform—all manufactured using TSMC’s 5nm node.

Breaking from its tradition of in-house production of mainstream platform CPUs, Intel’s decision to outsource to TSMC hints at potential future collaborations. This move opens doors to new opportunities for TSMC to handle the production of Intel’s mainstream laptop platforms.

It’s worth noting that the Intel Lunar Lake platform is scheduled for mass production at TSMC in the first half of next year, with a launch planned for the latter half of the year, targeting mainstream laptop platforms. Unlike the previous two generations of Intel laptop platforms, Lunar Lake integrates CPU, GPU, and NPU into a system-on-chip (SoC). This SoC is then combined with a high-speed I/O chip, utilizing Intel’s Foveros advanced packaging. Finally, the DRAM LPDDR5x is integrated with the two advanced packaged chips on the same IC substrate.

(Image: TSMC)

According to TechNews’ report, there are recent rumors indicating that AMD’s next-generation chip, with the Zen5C architecture codenamed “Prometheus,” will adopt a “Dual Foundry Mode.” This means it will simultaneously utilize TSMC’s 3nm and Samsung’s 4nm processes. This move suggests that AMD aims to diversify chip manufacturing, avoiding reliance solely on TSMC for its upcoming products.

Industry sources suggest that factors such as geopolitical considerations, negotiation tactics, and the overall semiconductor manufacturing ecosystem drive the search for secondary sources. AMD’s decision to employ a dual foundry approach is likely a strategic move to mitigate risks in this dynamic landscape.

Reportedly, Samsung’s 4nm process will primarily be utilized for the base version of Prometheus, while TSMC’s 3nm process will be employed for the high-end variant of Prometheus.

EXTREMETECH finds AMD’s move intriguing, speculating that it might stem from uncertainty about sourcing all chips exclusively from TSMC. This is significant for Samsung, historically excluded from the consumer tech and gaming sector. Since NVIDIA switched from Samsung to TSMC for the production of Ampere GPUs using the 8nm process, Samsung has been left out of the equation.

If the collaboration between AMD and Samsung proves successful, other companies may also consider shifting to Samsung. Reports suggest that AMD’s choice of Samsung’s 4nm process over the 3nm process could be attributed to potential yield challenges.

While it’s uncertain whether AMD will indeed implement the “Dual Foundry Mode,” the anticipation for the Zen5 architecture next year is high. Samsung is currently ahead of the industry in the adoption of GAA (Gate-All-Around) technology for its manufacturing processes, introducing GAA technology with their 3nm process ahead of others in the industry. TSMC, on the other hand, is anticipated making a similar change no earlier than 2025.

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• [News] A battle on 4nm: AMD Teams Up with Samsung, while Google Weighs Supplier Split

(Photo credit: AMD)