2020 was undoubtedly a milestone year in the development of TSMC, the leading semiconductor foundry. According to a report from TechNews, TSMC’s global expansion has reached locations in China, the United States, Japan, and Germany, solidifying its goal of being a “long-term and trustworthy provider of technology and capacity.”

On February 24th, TSMC will hold an opening ceremony for the Kumamoto plant, which is scheduled to commence production by the end of the year. With the opening of the Kumamoto plant, let’s review TSMC’s global expansion plan:

Arizona, United States

In May 2020, TSMC officially announced the selection of Arizona, United States, as the location for constructing an advanced process fab.

Initially planned to invest USD 12 billion, the facility aims to build a N5 process fab with a monthly capacity of 20,000 wafers. Construction was scheduled to commence in 2021, with mass production slated to begin by the end of 2024, creating approximately 1,600 job opportunities in the local area. Subsequently, in 2022, TSMC announced plans to start N4 advanced process production at the Arizona fab to meet market demands.

In December 2022, the second phase of construction began at the fab in Arizona, United States. It is expected to commence production using N3 process technology by 2026. The total investment for both phases amounts to approximately USD 40 billion, creating 4,500 jobs opportunities at TSMC.

Upon completion of both phases, the combined annual capacity will exceed 600,000 wafers, with the market value of end products estimated to exceed USD 40 billion. This project ranks as one of the largest foreign direct investment projects in US history.

However, due to the delay in the first phase’s production timeline from the end of 2024 to the first half of 2025, the production schedule for the second phase will also be postponed to start after 2027.

Kumamoto, Japan

In October 2021, TSMC, in collaboration with its customer Sony Group’s wholly-owned subsidiary, Sony Semiconductor Solutions, announced the establishment of a subsidiary called Japan Advanced Semiconductor Manufacturing (JASM) in Kumamoto, Japan. Sony Semiconductor Solutions plans to invest approximately USD 500 million to acquire up to 20% of the shares of JASM.

Following this, Denso, a major Japanese automotive components manufacturer, also announced its investment in JASM. TSMC further increased its investment in the Kumamoto plant, raising the investment amount to nearly JPY 1 trillion.

It plans to introduce 12/16-nanometer processes in addition to the originally planned 22/28-nanometer processes, with a monthly capacity reaching 55,000 wafers. This project has received commitments of support from the Japanese government, with an expected subsidy of approximately JPY 476 billion.

It was previously rumored that one of the shareholders of JASM, Sony Semiconductor, was urged by its customer, Apple, to expedite the production of image sensors (CIS) at the Kumamoto plant. Consequently, trial production began even before the opening of the Kumamoto plant. However, TSMC responded that the production timeline remains according to plan and is scheduled to commence before the end of 2024.

Recently, TSMC announced a new project in collaboration with its Japanese partners Sony Semiconductor, Denso Corporation, and Toyota Motor Corporation to invest in JASM and construct a second fab, scheduled to commence operations by the end of 2027.

TSMC stated that in response to customer demand, construction of the second JASM fab in Japan is slated to begin by the end of 2024. The expansion of production capacity is also expected to optimize the overall cost structure and supply chain efficiency of JASM.

In the future, the two fabs under JASM will enable a total monthly production capacity of over 100,000 12-inch wafers, providing 40-nanometer, 22/28-nanometer, 12/16-nanometer, and 6/7-nanometer processes for automotive, industrial, consumer, and high-performance computing (HPC) applications.

Capacity planning may be adjusted according to customer demand, with the Kumamoto plant directly creating a total of over 3,400 high-tech job opportunities. Through the investment, TSMC, Sony Semiconductor, Denso Corporation, and Toyota Motor Corporation hold approximately 86.5%, 6.0%, 5.5%, and 2.0% of the JASM shares, respectively.

Dresden, Germany

In August 2023, TSMC, along with Robert Bosch GmbH, Infineon Technologies AG, and NXP Semiconductors N.V., jointly announced plans to invest in the European Semiconductor Manufacturing Company (ESMC) located in Dresden, Germany, to provide advanced semiconductor manufacturing services.

TSMC stated that the ESMC represents a significant step forward in the construction of a 12-inch fab to support the future capacity demands in the rapidly growing automotive and industrial markets. The final investment decision is subject to confirmation of government subsidies.

This project is developed within the framework of the European Chips Act. Following approval by regulatory authorities and meeting other conditions, TSMC will hold a 70% stake in the joint venture, while Bosch, Infineon, and NXP will each hold a 10% stake. The fab will be operated by TSMC.

TSMC emphasized that the fab planned for this project is expected to utilize TSMC’s 28/22-nanometer Complementary Metal-Oxide-Semiconductor (CMOS) technology and 16/12-nanometer FinFET processes, with a monthly capacity of approximately 40,000 12-inch wafers.

Through advanced FinFET technology, the aim is to further strengthen the semiconductor manufacturing ecosystem in Europe and create approximately 2,000 direct high-tech job opportunities. ESMC aims to commence construction of the fab in the second half of 2024, with production slated to begin by the end of 2027.

Continuing Advancements in Advanced Processes in Taiwan

In addition to its overseas expansions, TSMC continues to advance its most cutting-edge processes and advanced packaging technologies in Taiwan.

Given the strong demand for N3 process technology over the years, TSMC is expanding the N3 process capacity at its Tainan Science Park. Additionally, in preparation for the commencement of mass production of N2 process technology in 2025, TSMC plans to establish multi-stage N2 process technology capacity in the science parks of Hsinchu and Kaohsiung.

In Hsinchu’s Baoshan area, the first phase has been completed, and TSMC’s Global R&D Center has been in use since 2023. Baoshan Phase Two will serve as the base for TSMC’s N2 process technology.

Additionally, TSMC plans to construct two 2-nanometer advanced process fabs in Kaohsiung. The related land pollution remediation projects are expected to be completed by the end of 2024.

Finally, regarding the urban planning amendment for the expansion of the Central Taiwan Science Park Phase II, which concerns TSMC’s layout for constructing 2-nanometer fabs, TSMC also indicated that the review progress by the Taichung Science Park Administration is proceeding as scheduled.

This development will allow the land in the Central Taiwan Science Park to be handed over to TSMC for use as early as 2024, enabling subsequent commencement of the construction of the fabs.

Read more

• [News] Intel Foundry Unveils its Expanded Process Roadmap for AI Era at Direct Connect 2024 Event
• Strategic Collaboration Between Intel and UMC to Optimize FinFET Foundry Market with Existing Resources, Says TrendForce

(Photo credit: Intel)

South Korean memory giant SK Hynix has confirmed record-breaking sales of High Bandwidth Memory (HBM) over the past few months, driving profitability in the fourth quarter and predicting an industry-wide recovery.

According to Wccftech, SK Hynix Vice President Kim Ki-tae stated on February 21st that the demand for HBM, as an AI memory solution, is experiencing explosive growth as generative AI services become increasingly diverse and continue to evolve.

The report has cited insights from Kim Ki-tae, who stated, “HBM, with its high-performance and high-capacity characteristics, is a monumental product that shakes the conventional wisdom that memory semiconductors are only a part of the overall system. ”

Kim Ki-tae also mentioned that despite ongoing external uncertainties, the memory market is expected to gradually warm up in 2024. This is attributed to the recovery in product demand from global tech giants.

Moreover, AI devices such as PCs or smartphones are expected to increase the demand for artificial intelligence. This surge is anticipated to boost the sales of HBM3E and potentially drive up the demand for products like DDR5 and LPDDR5T.

Kim Ki-tae emphasized that their HBM products have already sold out for this year. Although it’s just the beginning of 2024, the company has already begun gearing up for 2025.

SK Hynix Plans to Establish Advanced Packaging Plant in the US

SK Hynix is reportedly set to establish an advanced packaging plant in Indiana, with the US government aiming to reduce dependence on advanced chips from Taiwan.

As per the Financial Times on February 1st, citing unnamed sources, SK Hynix’s rumored new packaging facility in Indiana may specialize in 3D stacking processes to produce HBM, which will also be integrated into NVIDIA’s GPUs.

Currently, SK Hynix produces HBM in South Korea and then ships it to Taiwan for integration into NVIDIA GPUs by TSMC.

Read more

• [News] Reports Suggest SK Hynix to Establish Advanced Packaging Facility in the US
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(Photo credit: SK Hynix)

As Intel’s January announced the collaboration with UMC on the 12-nanometer process platform, UMC’s Co-General Manager, Jason Wang, led a team to support Intel’s IFS event.

Cited by Commercial Times in its report, Wang emphasized that UMC’s existing customers would have more production location options and benefit from the platform strategy. UMC will seamlessly transition from the 28/22-nanometer to the critical 12-nanometer.

Followed by joint interviews to share insights into the future strategies of both parties, Wang stated that in the face of rapid changes and challenges in the external environment, industries need to strengthen their cooperative relationships and seize opportunities for collaboration.

Intel and UMC announced their collaboration at the end of January, focusing on the development of a shared platform for the 12-nanometer process. In the future, UMC will be able to expand its orders for the front-end of the 12-nanometer process, while Intel will secure orders for the 12-nanometer wafer manufacturing.

Jason Wang emphasized that UMC has a comprehensive solution for the 28/22-nanometer, with demand trending towards stability. However, due to past limitations in resource allocation , UMC has paused at the 14/16-nanometer. Advancing to more advanced processes is just a matter of timing.

Wang further stated that both parties will focus on creating customer value, breaking frameworks, and innovating in cooperation. The two companies complement each other’s strengths, accelerating the timeline for technological development and expanding their global footprint.

Wang revealed that Intel has already included UMC’s 12-nanometer process in its product roadmap and has begun deep collaboration. UMC has deployed personnel to oversee this, with Intel leveraging UMC’s know-how in management.

Additionally, the collaboration involves revenue sharing rather than the rumored licensing fees. They anticipate completing the Process Design Kit (PDK) by next year and achieving mass production by the end of 2026.

Overall, TrendForce views this alliance as a significant step. UMC brings its plentiful experience in mature processes, while Intel contributes its advanced technological prowess.

This partnership is not just about mutual benefits at the 10nm process level; it’s a watchpoint for potentially deeper and more extensive collaboration in their respective fields of expertise. In the dynamic world of semiconductor manufacturing, this Intel-UMC alliance is a fascinating development to keep an eye on.

Read more

• [News] Intel Foundry Unveils its Expanded Process Roadmap for AI Era at Direct Connect 2024 Event
• Strategic Collaboration Between Intel and UMC to Optimize FinFET Foundry Market with Existing Resources, Says TrendForce

(Photo credit: Intel)

Pat Gelsinger, CEO of Intel, announced on February 22nd that Intel will expand its orders to TSMC, as per a report by Commercial Times.

Following the IFS Direct Connect event in San Jose, USA, Gelsinger pointed out in an interview that two generations of CPU Tiles would be manufactured using TSMC’s N3B process,  marking the official arrival of Intel CPU orders for laptop platforms. 

Gelsinger’s interview confirms that Intel has indeed expanded its outsourcing orders to TSMC. Currently, TSMC is responsible for producing Intel CPUs, GPUs, and NPUs tiles for the Arrow and Lunar Lake platforms.

As per Intel’s product roadmap, Arrow Lake will utilize the Intel 20A process, while Lunar Lake will utilize the 18A process, both incorporating transistor designs such as PowerVia and RibbonFET.

Gelsinger previously stated that Intel Foundry is striving to become the world’s second-largest foundry by 2030. The objective is to fill the fabs and supply the widest range of customers globally, including competitors like NVIDIA and AMD.

According to TrendForce’s data statistics for the third quarter of 2023, the world’s top three foundries were TSMC, Samsung, and GlobalFoundries, with Intel Foundry Services (IFS) ranking ninth at the time.

As for rumors about the US government considering providing over USD 10 billion in subsidies, he disclosed that they expect to receive chip legislation subsidies very soon, although the exact amount is yet to be announced.

Read more

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• [News] Intense Competition with Samsung and Intel in Advanced Processes; TSMC Speeds Up 2nm Progress

(Photo credit: Intel)

Kevin Zhang, Senior Vice President of Business Development at TSMC, introduced the company’s latest technologies at the International Solid-State Circuits Conference (ISSCC) 2024. According to TechNews citing from the speech, Zhang shared insights into future technological advancements, prospects for advanced processes, and the latest semiconductor technologies needed in various fields.

Zhang noted that since the introduction of ChatGPT and Wi-Fi 7, a lot of advanced semiconductor are required, as we are entering an accelerated growth period for semiconductor going forward.

In the automotive sector, the industry is undergoing a revolution, with many suggesting that new vehicles will be software-defined. However, Zhang believes it’s more about silicon-defined because software needs to run on silicon, driving the future of autonomous driving capabilities.

CFET (Complementary Field-Effect Transistor)

In terms of technology, Transistor remain at the heart of the innovation, silicon innovation. It has shifted from geometry reduction to architectural innovation and the use of new materials. Moving from 16-nanometer FinFET to today’s 2-nanometer Nano Sheet technology represents significant progress in high-performance computing and architectural innovation.

What’s next? The answer is CFET.

Kevin Zhang explained that CFET involves stacking nMOS and pMOS on top of each other, significantly improving component currents and increasing transistor density by 1.5 to 2 times.

Alternatively, efforts are being made to create higher-performance switching devices from low-dimensional materials such as 2D materials, surpassing today’s devices or transistors.

Kevin Zhang also showcased that TSMC has successfully fabricated CFET architectures in the laboratory, stating, “This is a real integrated device that has been fabricated in our lab. Here, you see the transistor IV curve. They are beautiful curves. So, this is a significant milestone in terms of continuing to drive the innovation of the transistor architecture.”

However, as the geometry of the transistor shrinks, it becomes increasingly difficult and costly. This necessitates collaboration between process development teams and design research to achieve optimal benefits, known as “Design-Technology Co-Optimization” (DTCO).

In addition, TSMC has introduced FINFLEX technology, enabling chip designers to choose and mix the best fin structures to support each critical functional block, achieving optimal performance, density, and power consumption.

Another example of DTCO is Static Random Access Memory (SRAM). SRAM has scaled from 130 nanometers to the current 3 nanometers, and TSMC has achieved a over 100x density improvement, a result of collaboration or combination of a process innovation and adoption of the more advanced design technique.

Nevertheless, the essence or the objective of this technology scaling is for “energy efficient compute,” as Kevin Zhang expressed. He stated that in the entire semiconductor industry, TSMC has come a long way, and this progress has made today’s AI possible.

• Advancements in HPC/AI Technology Platforms: 3D Stacking, Silicon Photonics, CPO

Whether it’s GPUs, TPUs, or customized ASICs, they all feature this particular integration scheme. Currently, the mainstream is 2.5D packaging. However, to meet future high-performance computing demands, this platform needs significant enhancement, requiring higher density and lower power consumption computation.

Therefore, stacking is needed, including integrating many memory bandwidths and HBM into the package, while considering issues such as power supply, I/O, and interconnect density.

Consequently, Kevin Zhang stated that bringing “silicon photonics into packaging” is the future direction. However, this will face many challenges, such as Co-Packaged Optics (CPO) closer to the electronic side.

1. 3D Stacking

When it comes to 3D stacking, Kevin Zhang presented a diagram and explained that to achieve higher interconnect density, specifically Chip-to-Chip connections, 3D stacking allows the bonding pitch to scale to just a few micrometers, achieving interconnect density like monolithic. “That’s why the 3D (stacking) is the future,” he concluded.

2. Silicon Photonics / Co-Packaged Optics (CPO)

Kevin Zhang pointed out that while electronics excel at computation, photons are better for signaling or communication. He illustrated that if a 50 terabyte switch, an all-electronic copper system were used, it would consume 2,400 W.

The current solution involves using pluggable modules, which can save 40% of power (> 1500W). However, as the need for higher-speed signals and larger bandwidths increases in the future, this solution falls short. Therefore, integrating silicon photonics technology is necessary to introduce photon capabilities.

• Automotive Technology

1. Pursuing Low DPPM

Fundamentally, the latest automotive technologies require significant computational power, but power consumption is becoming a concern, especially for battery-powered vehicles.

Kevin Zhang states that automotive semiconductor technology has lagged behind consumer or HPC technologies by several generations due to stringent safety requirements. The DPPM (Defects Per Million) for automotive applications must be close to zero.

Therefore, fabs, semiconductor manufacturers, and automotive designers must collaborate more closely to accelerate this pace. He also promises, “you will see 3 nanometer in your car before long.”

2. MRAM/RRAM

As automotive transitions to a domain architecture, MCUs (Microcontroller Units) become increasingly important and require advanced semiconductor technology to provide computational capabilities.

Traditional MCUs mostly rely on floating-gate technology, but this technology encounters bottlenecks below 28 nanometers. Fortunately, the industry has invested in new memory technologies, including new non-volatile memories such as Magnetic Random Access Memory (MRAM) or Resistive Random Access Memory (RRAM).

Therefore, transitioning from MCU to MRAM or RRAM-based technologies helps drive continuous technology scaling from 28 nanometers to 16 nanometers, or even 7 nanometers.

• Sensor and Display: CIS (CMOS Image Sensors)

Sensor technology has evolved from simple 2D designs and single layer design to intelligent systems with 3D wafer stacking, essentially layering the signal processing on top of the sensing layer.

Kevin Zhang also mentioned, “our technologies already start investing, researching on the multi-layer design.”

Engaging in three or more layer designs allows for the optimization of pixels, continuing the trend of scaling pixel sizes while meeting resolution requirements and achieving optimal sensing capabilities simultaneously.

Another example is AR (Augmented Reality) and VR (Virtual Reality), where separating memory layers and stacking them onto other logic chips can effectively reduce size while maintaining high-performance demands.

Read more

• [News] TSMC Reportedly Doubles CoWoS Capacity while Amkor, ASE also Enter Advanced Packaging for AI
• [News] Intense Competition with Samsung and Intel in Advanced Processes; TSMC Speeds Up 2nm Progress

(Photo credit: TSMC)