Rumors swirl around AMD’s upcoming chip architecture, codenamed “Prometheus,” featuring the Zen 5C core. As reported by TechNews, the chip is poised to leverage both TSMC’s 3nm and Samsung’s 4nm processes simultaneously, marking a shift in the competitive landscape from process nodes, yield, and cost to factors like capacity, ecosystem, and geopolitics, are all depends on customer considerations.

Examining yields, TSMC claims an estimated 80% yield for its 4nm process, while Samsung has surged from 50% to an impressive 75%, aligning with TSMC’s standards and raising the likelihood of chip customers returning. Speculation abounds that major players such as Qualcomm and Nvidia may reconsider their suppliers, with industry sources suggesting Samsung’s 4nm capacity is roughly half of TSMC’s.

Revegnus, a reputable X(formerly Twitter) source, unveiled information from high-level Apple meetings, indicating a 63% yield for TSMC’s 3nm process but at double the price of the 4nm process. In the 4nm realm, Samsung’s yield mirrors TSMC’s, with Samsung showing a faster-than-expected yield recovery.

Consequently, with Samsung’s significant improvements in yield and capacity, coupled with TSMC’s decision to raise prices, major clients may explore secondary suppliers to diversify outsourcing orders, factoring in considerations such as cost and geopolitics. Recent reports suggest Samsung is in final negotiations for a 4nm collaboration with AMD, planning to shift some 4nm processor orders from TSMC to Samsung.

Beyond AMD, the Tensor G3 processor in Google’s Pixel 8 series this year adopts Samsung’s 4nm process. Samsung’s new fabs in Taylor, Texas, sees its inaugural customer in its Galaxy smartphones, producing Exynos processors.

Furthermore, Samsung announced that U.S.-based AI solution provider Groq will entrust the company to manufacture next-generation AI chips using the 4nm process, slated to commence production in 2025, marking the first order for the new Texas plant.

Regarding TSMC’s 4nm clients, alongside longstanding partners like Apple, Nvidia, Qualcomm, MediaTek, AMD, and Intel, indications propose a potential transition to TSMC’s 4nm process for Tensor G4, while Tensor G5 will be produced using TSMC’s 3nm process. Ending the current collaboration with Samsung, TSMC’s chip manufacturing debut is anticipated to be delayed until 2025.

Last year, rumors circulated about Tesla, the electric vehicle giant, shifting orders for the 5th generation self-driving chip, Hardware 5 (HW 5.0), to TSMC. This decision was prompted by Samsung’s lagging 4nm process yield at that time. However, with Samsung’s improved yield, industry inclination leans towards splitting orders between the two companies.

On August 7th, HuaHong Group officially went public on the Sci-Tech Innovation Board Market, Shanghai Stock Exchange (STAR Market, SSE). Combined with the return of SMIC to A-shares (China’s domestic shares) in the past two years and Nexchip’s listing in May, it brings together the three major players in China’s foundry sector on the STAR Market. Additionally, SMEC, closely linked to SMIC, also went public on the STAR Market without turning a profit. Overall, China’s foundry industry is steadily gaining strength.

As per TrendForce’s latest research, challenges in the economic outlook and ongoing inventory issues this year have led to a slowdown in demand. This is particularly noticeable in the automotive and industrial control, where inventory has been piling up after short-term fulfillment. Fabless and other IDM inventory digestion have faced severe restrictions. IDM foundries, launching new capacities, are consolidating outsourced orders and once again reducing orders to foundries. In 2024, given the expected unfavorable economic environment, the overall recovery of capacity utilization poses challenges.

While Chinese foundries have not been immune to these challenges, the losses have been mitigated thanks to the boost in China’s import substitution policies on semiconductors. According to TrendForce, the global ratio of mature (>28nm) to advanced (<16nm) processes is projected to hover around 7:3 from 2023 to 2027. Propelled by policies and incentives promoting local production and domestic IC development, China’s mature process capacity is anticipated to grow from 29% this year to 33% by 2027. Leading the charge are giants like SMIC, HuaHong Group, and Nexchip.

Exploring China’s Wafer Foundries Landscape

According to TrendForce, excluding 7 temporarily suspended fabs, China currently operates 44 fabs (25 fabs in 12-inch, 4 fabs in 6-inch wafers, and 15 in 8-inch fabs and production lines), additionally, 22 fabs are under construction (15 fabs in 12-inch, and 8 fabs in 8-inch). In the future, SMIC, Nexchip, CXMT, and Silan plan to construct 10 fabs (9 fabs in 12-inch, and 1 fab in 8-inch). Overall, by the end of 2024, China aims to establish 32 large fabs, and all of them are about to focus on mature processes.

Reviewing the distribution of wafer foundries across China, the Yangtze Delta region hosts nearly half of the total, with significant concentrations in provinces like Shanghai, Wuxi, Beijing, Hefei, Chengdu, and Shenzhen.

Nearly 4.14 million wafer capacity in 12-inch will be ongoing per month in China until 2026

In terms of capacity, the statistics showed that China currently operates 31 fabs in 12-inch, including those under construction with fixed capacity for 12-inch. The total monthly capacity is approximately 1.189 million wafer capacity. Compared to the planned monthly capacity of 2.17 million wafer capacity, the capacity utilization of these fabs is close to 54.48%, still a significant room for expansion.

Considering construction and future planning, it is anticipated that China will add 24 fabs in 12-inch in the next five years, with a planned monthly capacity of 2.223 million wafer capacity. Assuming all planned 12-inch wafer foundries achieve full production, by the end of 2026, the total monthly capacity of 12-inch in China will exceed 4.14 million wafer capacity, marking a 248.19% increase compared to the current capacity utilization rate.

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• TrendForce Foresees China’s Mature Wafer Processes to Expand to 33% by 2027, Japan Secures Advanced Processes

Mature process foundries are locked in a battle to uphold a 60% capacity utilization rate. Reports indicate that major players, including UMC, Vanguard International Semiconductor (VIS), and PSMC, are slashing prices significantly for the first quarter of the coming year to salvage their capacity utilization rates. This reduction, reaching double-digit percentages and up to 15% to 20% for project customers, stands out as the most extensive post-pandemic price cut, according to UDN News.

Post-Pandemic Price Challenges in Mature Process Foundries    

This pricing adjustment is pushing the prices of mature process foundries to a new low post-pandemic, affecting the profit margins and profitability trends of related companies. Industry sources disclose that only TSMC’s prices remain robust, with almost no exception for other foundries.

To rescue capacity utilization rates, companies are aggressively tweaking their quotes. A source from an IC design company privately reveals that foundries have notified them of slow-moving business in mature processes, resulting in a direct drop in capacity utilization rates. To ensure capacity utilization rates and market share, maintaining a certain level of production scale becomes imperative, prompting a substantial reduction in quotes.

Industry sources emphasize that despite recent indications of recovery in the PC and smartphone markets, clients remain cautious due to external factors such as inflation, especially given almost a year of inventory clearance. Companies, still on edge, fear slipping back into the challenges of inventory clearance and thus maintain a conservative approach to order placement.

Currently, the recovery in order placement strength is only about 30% to 40% of pre-pandemic levels, compelling wafer foundries to intensify their price cuts to prevent orders from being lost to competitors willing to lower prices, resulting in even lower capacity utilization.

It is evident that consumer IC demand for foundry services is low, and whom focusing on 8-inch mature process are the most affected. It is mainly due to excessive duplicate orders from integrated device manufacturers (IDMs) and IC design companies in the past, leading to inventory clearance for chips such as power management ICs, driver ICs, and microcontrollers (MCUs). Some products have even shifted to 12-inch wafers, keeping the capacity utilization rates of 8-inch foundries at a low level.

Navigate Semiconductor Shifts in TSMC, UMC, VIS, and PSMC

Industry sources note that TSMC is bolstered by advanced processes, enabling them to bundle them with mature processes for sale. Moreover, TSMC’s pricing strategy for mature processes has not surged as dramatically as that of other related companies, making it more acceptable to customers.

As for UMC, the company anticipates a drop in capacity utilization rates from 67% in the last quarter to 60% to 63% in this quarter, reaching a single-season low in recent years. Due to the continuous adjustment of capacity utilization rates, the gross profit margin will drop from 35.9% last quarter to 31% to 33%, reverting to levels seen at the beginning of the pandemic in 2021.

In response to pricing issues, UMC stated that, as mentioned in a recent earnings call, there will indeed be a significant decrease in the 8-inch, but there will be no adjustments for the 12-inch. Supply chain sources reveal that UMC has reportedly offered a 5% concession, aiming to consolidate order momentum with major clients this quarter. Considering the anticipated weak demand in the first quarter of next year and to attract more order placements, UMC plans to expand the price reduction to double-digit percentages.

According to the supply chain, VIS is expected to see a price reduction of up to 5% in the second half of the year. Large-volume clients may even secure a 10% discount, with a further decrease expected in the first quarter of next year, ranging from single to double-digit percentages. The company’s management previously mentioned at a conference call that, in response to intense price competition, short-term flexible adjustments are anticipated.

Similarly impacted by conservative customer order placements, PSMC reported losses in the third quarter, with capacity utilization rates hovering around 60%. It is reported that PSMC is also gearing up to implement price reduction measures to enhance capacity utilization rates.

(Image: VIS)

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Mainland China’s 3D NAND flash memory manufacturer, Yangtze Memory Technologies Co. (YMTC), filed a lawsuit against the U.S. memory chip leader, Micron Technology, on November 9th in the Northern District Court of California. The lawsuit accuses Micron of infringing upon eight of YMTC’s U.S. patents related to 3D NAND technology.

According to ICsmart, the patents involved in this case from YMTC include US10,950,623 (3D NAND memory device and method of forming the same), US11,501,822 (Non-volatile storage device and control method), US10,658,378 (Through-array contact [TAC] for three-dimensional memory devices), and US10,937,806 (Through-array contact [TAC] for three-dimensional memory devices), US10,861,872 (Three-dimensional memory device and method for forming the same), US11,468,957 (Architecture and method for NAND memory operation), US11,600,342 (Method for reading three-dimensional flash memory), and US10,868,031 (Multiple-stack three-dimensional memory device and fabrication method  thereof).

In the complaint, YMTC alleges that Micron’s 128-layer, 176-layer, and other series of 3D NAND technology have violated eight patents owned by YMTC. Micron is accused of using YMTC’s patented technology without authorization to compete with YMTC, protecting market share and impeding YMTC’s interests, thereby inhibiting innovation.

In recent years, with the stacking of 3D NAND technology reaching 128 layers and even higher, the chip area occupied by peripheral CMOS circuits may exceed 50%. To address this issue, YMTC introduced its proprietary innovative Xtacking technology in 2018.

Established in July 2016 and headquartered in Wuhan, Hubei, YMTC is an IDM (Integrated Device Manufacturer) specializing in the design and manufacturing of 3D NAND flash memory. It also provides comprehensive memory solutions.

Under the shadow of the ongoing US-China tech rivalry, Micron Technology adopted a low-key approach at this year’s Import Expo in Shanghai. During a meeting with Micron’s CEO, Sanjay Mehrotra, Chinese Minister of Commerce Wang Wentao on November 1st welcomed Micron’s continued presence and expansion in the Chinese market, emphasizing the importance of adhering to Chinese laws and regulations for sustainable development. Mr. Mehrotra expressed the company’s willingness to further invest in China.

However, on May 21st this year, China’s Cyberspace Administration announced serious cybersecurity issues with Micron’s products sold in China. These products didn’t pass the review, leading Chinese operators to halt the purchase of Micron’s products. This indicates a potential ban on Micron’s products in the Chinese market.

In October 2022, the US imposed exprt restrictions on advanced chip manufacturing equipment, including placing 36 Chinese companies such as YMTC on an entity list.

(Photo credit: iStock)

The demand for TSMC’s CoWoS advanced packaging is skyrocketing. Following NVIDIA’s expansion confirmation in October, there are reports in the industry that major clients like Apple, AMD, Broadcom, Marvell, and others are also placing additional orders with TSMC.

To meet the demands of these five major clients, TSMC is fast-tracking the expansion of CoWoS advanced packaging capacity. Next year, the monthly capacity will increase by about 20% more than the original doubling target, reaching 35,000 wafers, reported by UDN News.

TSMC has not commented on the capacity deployment for CoWoS advanced packaging. Industry sources believe that the substantial orders from TSMC’s major clients indicate a widespread growth in AI applications, driving the demand for chips such as GPU and AI accelerators.

In response to the continuous increase in AI demand, TSMC had previously announced the doubling of CoWoS advanced packaging capacity expansion for next year but did not disclose the monthly production capacity. Industry reports suggest that TSMC’s CoWoS advanced packaging capacity next year will not only double but will also increase by an additional 20% from the original target, resulting in a total monthly capacity of 35,000 wafers.

NVIDIA currently stands as the main large customer for TSMC’s CoWoS advanced packaging, securing almost 60% of TSMC’s related capacity, which is used in its AI chips such as H100 and A100. Additionally, AMD’s latest AI chip products are in the mass production stage, and the upcoming MI300 chip, expected to launch next year, will adopt both SoIC and CoWoS advanced packaging.

At the same time, Xilinx, a subsidiary of AMD, has been a significant customer for TSMC’s CoWoS advanced packaging. With the continuous growth in AI demand, not only Xilinx but also Broadcom has started increasing orders for TSMC’s CoWoS advanced packaging capacity.

(Image: TSMC)

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