SK Hynix CEO Kwak Noh-Jung expressed optimism at the Consumer Electronics Show (CES) in the United States, stating that artificial intelligence (AI) chips would propel SK Hynix’s market value to double within three years, reaching KRW 200 trillion (approximately USD 152 billion).

Kwak also revealed plans to adjust the DRAM production reduction policy in the first quarter, while anticipating changes in NAND Flash production strategy in the latter half of the year.

At the CES exhibition in Las Vegas, Kwak emphasized that generative AI is gradually becoming widespread, and memories are increasingly crucial. With the advancement of AI systems, customer demands for memory will become more diverse. Kwak highlighted the development of a platform to offer customized options for various customers.

“If we prepare the products we are currently producing well, pay attention to maximising investment efficiency and maintaining financial soundness, I think we can attempt to double the current market capitalisation of 100 trillion won to 200 trillion won within three years,” Kwak said.

Kwak further stated in the CES: “There are only three HBM providers in the market. What I can say for sure is that SK Hynix is a clear leader in the HBM space.”

For the current HBM market, as reported by TrendForce earlier, SK hynix holds the lead in HBM3 production, serving as the principal supplier for NVIDIA’s server GPUs.

Samsung, on the other hand, is focusing on satisfying orders from other CSPs. The gap in market share between Samsung and SK hynix is expected to narrow significantly in 2023 due to an increasing number of orders for Samsung from CSPs. Both firms are predicted to command similar shares in the HBM market sometime between 2023 to 2024—collectively occupying around 95%.

Meanwhile, when asked if SK Hynix would ease its current chip production reduction policy, Kwak responded that the company’s policies are flexible and will be adjusted based on different product categories.

He mentioned that SK Hynix might change its DRAM production reduction policy in the first quarter, while adjustments for NAND Flash are anticipated to take place in the latter half of the year.

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(Photo credit: SK Hynix)

ASML, a key chipmaking equipment supplier, is reported to have its incoming CEO, Christophe Fouquet, visiting Taiwan soon. According to Commercial Times citing from supply chain sources, it’s suggested that he will meet with TSMC and other related suppliers to discuss next-generation EUV equipment.

In 2008, Christophe Fouquet joined ASML, holding various management positions. He currently serves as Executive Vice President and Chief Business Officer. In April, he will succeed CEO Peter Wennink, who has held the position since July 2013, upon Wennink’s retirement at the completion of his term.

The high-level visit from ASML’s management to TSMC raises questions about whether it pertains to potential orders for the new “High-NA EUV” (High Numerical Aperture Extreme Ultraviolet Lithography System). TSMC has yet to confirm this, but the company is exploring various possibilities, including investments in advanced packaging.

Industry sources indicate that the cost of High-NA EUV exceeds USD 300 million. Considering the cost-effectiveness balance, TSMC is not in a hurry to adopt it. The primary reason is the imminent need to establish a plant in the United States. It is estimated that future capital expenditures will significantly lean towards expanding production facilities overseas.

Under the U.S. chip export restrictions, ASML halted the shipment of EUV equipment to China in 2019. Under continued pressure from the U.S., the company recently canceled some shipments of Deep Ultraviolet Lithography equipment (DUV) to China.

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(Photo credit: ASML)

TSMC’s foundry in Kumamoto, Japan, has been completed. Currently, the tool-in is underway, with a grand opening ceremony scheduled for February 24^th, 2024.

Following this, trial production will commence, with mass production expected by the year-end. The Taiwanese semiconductor supply chain is optimistic about TSMC’s continued investment in local facilities, with plans for establishing service points in Japan.

According to reports from Japanese news source Kyodo News, TSMC’s Kumamoto plant is operated by its Japanese subsidiary, Jasm. Construction commenced in April 2022, with a 24-hour rush to completion. The office building facilities were inaugurated in August 2023, and the four-story, two-basement fab was also completed by the end of last year. The cleanroom’s total area, where production takes place, is approximately 45,000 square meters.

After the grand opening ceremony of TSMC’s Kumamoto plant, trial production will begin, with mass production scheduled by the end of this year. The plant aims to produce 22/28nm and 12/16nm process chips, targeting a monthly capacity of 55,000 wafers. Joint venture partners at the facility include Sony’s subsidiary Sony Semiconductor Solutions and Denso.

According to Japanese media Nikkei Asia, TSMC is currently assessing the construction of a second plant in Kumamoto. The estimated total investment for this new facility is around JPY 2 trillion, and the Japanese Ministry of Economy, Trade, and Industry is considering a subsidy of approximately JPY 900 billion, surpassing the amount for the first plant. TSMC plans to utilize the Kumamoto Fab 2 for the production of 6nm chips. There is potential for further investment in a third plant in the future.

As per a report from Liberty Times Net, with optimism for TSMC’s opportunities in Japan, Taiwan’s semiconductor supply chain is establishing service points in the country.

Cleanroom and MEP (Mechanical, Electrical, Plumbing) integration engineering service provider, Marketech International Corp., has set up a subsidiary in Japan to cater to major clients. Topco Scientific Co. has established SHUNKAWA CO., LTD. in Japan and a branch in Kumamoto to offer specialized chemical warehouse services to major clients.

Analytical testing facility, MA-tek, established a lab in Nagoya over four years ago and expanded with a second lab in Kumamoto last September due to increased demand. Following suit, MSSCORPS Co. plans to establish a testing and analytical center in Tokyo, Japan.

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(Photo credit: TSMC)

In the intense battle of AI chips between NVIDIA and AMD this year, AMD’s MI300 has entered mass production and shipment 1H24, gaining positive adoption from clients. In response, NVIDIA is gearing up to launch upgraded AI chips. TSMC emerges as the big winner by securing orders from both NVIDIA and AMD.

Industry sources have revealed optimism as NVIDIA’s AI chip shipment momentum is expected to reach around 3 million units this year, representing multiple growth compared to 2023.

With the production ramp-up of the AMD MI300 series chips, the total number of AI high-performance computing chips from NVIDIA and AMD for TSMC in 2024 is anticipated to reach 3.5 million units. This boost in demand is expected to contribute to the utilization rate of TSMC’s advanced nodes.

According to a report from the Economic Daily News, TSMC has not commented on rumors regarding customers and orders.

Industry sources have further noted that the global AI boom ignited in 2023, and 2024 continues to be a focal point for the industry. A notable shift from 2023 is that NVIDIA, which has traditionally dominated the field of high-performance computing (HPC) in AI, is now facing a challenge from AMD’s MI300 series products, which have begun shipping, intensifying competition for market share.

Reportedly, the AMD MI300A series products have commenced mass production and shipment this quarter. The central processing unit (CPU) and graphics processing unit (GPU) tile are manufactured using TSMC’s 5nm process, while the IO tile use TSMC’s 6nm process.

These chips are integrated through TSMC’s new System-on-Integrated-Chip (SoIC) and Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technologies. Additionally, AMD’s MI300X, which does not integrate the CPU, is also shipping simultaneously.

Compared to NVIDIA’s GH200, which integrates CPU and GPU, and the H200, focusing solely on GPU computation, AMD’s new AI chip performance exceeds expectations. It offers a lower price and a high cost-performance advantage, attracting adoption by ODMs.

In response to strong competition from AMD, NVIDIA is upgrading its product line. Apart from its high-demand H200 and GH200, NVIDIA is expected to launch new products such as B100 and GB200, utilizing TSMC’s 3nm process, by the end of the year.

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(Photo credit: NVIDIA)

Intel recently announced that it has acquired the market’s first ASML Extreme Ultraviolet (EUV) exposure equipment with a 0.55 Numerical Aperture (High-NA), aiming to advance its chip manufacturing technology in the coming years. In contrast, TSMC appears to be taking a more cautious approach, currently showing no urgency to join the race for this next-generation exposure technology.

The High-NA EUV exposure equipment obtained by Intel will initially be used for learning and mastering the technology, with plans to implement it in the Intel 18A process node in the next two to three years. 

Industry sources suggest that unlike Intel’s plan to introduce High-NA EUV and GAA transistors simultaneously in the Intel 18A process technology, it is anticipated that TSMC may not adopt this technology until the 1.4nm (A14) node, possibly in 2030 or later.

According to a report from IThome, in fact, Intel’s proactive development roadmap includes implementing the RibbonFET gate-all-around (GAA) transistor architecture and PowerVia backside power delivery technology starting from the Intel 20A process.

Subsequently, further optimizations are expected in the Intel 18A process, followed by the adoption of High-NA EUV exposure equipment in subsequent process nodes after Intel 18A. These advancements is anticipated to achieve lower power consumption, higher performance, and smaller chip sizes.

In addition, Intel plans to introduce pattern shaping starting from the 20A process, followed by the adoption of High-NA EUV after the 18A node. This approach is expected to reduce the complexity of the manufacturing process and avoid the use of EUV double patterning.

However, some professionals in the industry have stated that, at least in the initial stages, the cost of High-NA EUV may be higher than that of Low-NA EUV. Furthermore, High-NA EUV lithography equipment present a series of specific challenges too, including a halving of the exposure area.

These are two of the reasons why TSMC is currently adopting a cautious approach. TSMC tends to favor the use of cost-effective mature technologies to ensure product competitiveness.

In fact, If we look back at the development of EUV technology, TSMC began using EUV exposure equipment in chip production as early as 2019, a few months later than Samsung but several years ahead of Intel. Currently, Intel is expected to take the lead in the High-NA EUV field ahead of Samsung and TSMC to gain a certain technological and strategic advantage, increasing its appeal to customers.

Therefore, whether TSMC can maintain its leading position in process technology, especially if it adopts High-NA EUV exposure machines later than competitors, remains subject to ongoing observation.

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(Photo credit: ASML)