Despite facing economic challenges and the impact of high inflation, the flash memory market finds itself in a challenging period. Nevertheless, major DRAM manufacturers continue the pursuit of advanced technology.

For DRAM chips, advanced manufacturing processes mean improved energy efficiency, increased capacity, and an enhanced end-user experience. Currently, in the world of advanced DRAM processes, such as the 10nm class, has reached the fifth generation. Micron refers to it as 1β DRAM, while Samsung calls it 1b DRAM.

Since Micron commenced production of 1β DRAM last October, they have set their sights on producing 1γ DRAM by 2025. This will mark Micron’s first foray into extreme ultraviolet (EUV) lithography technology, and for now, EUV production is centered in their Taichung facility in Taiwan. Therefore, the 1γ process is expected to kick off production there, with potential expansion to their Japanese facilities in the future. Samsung, on the other hand, plans to enter the 1bnm process stage in 2023, achieving chip capacities ranging from 24Gb (3GB) to 32Gb (4GB) and native speeds of 6.4 to 7.2Gbps.

In the NAND Flash business, the technology has now exceeded the remarkable milestone of 200-layer stacking, with storage manufacturers relentlessly striving for even higher layer counts. On August 9th, SK Hynix showcased the world’s first 321-layer NAND Flash memory sample during the 2023 Flash Memory Summit. This innovation has increased efficiency by 59% compared to the previous 238-layer 512Gb NAND. SK Hynix plans to further refine the 321-layer NAND Flash and intends to commence production in the first half of 2025.

Furthermore, Micron has ambitious plans beyond 232 layers, with products like 2YY, 3XX, and 4XX on the horizon. Kioxia and Western Digital are also actively exploring 3D NAND technology with more than 300, 400, and 500 layers. Samsung is planning to introduce the ninth generation of 3D NAND in 2024, possibly featuring 280 layers, followed by the tenth generation in 2025-2026, potentially reaching 430 layers. Their ultimate goal is to achieve 1000-layer NAND Flash by 2030.

(Image: SK Hynix)

As semiconductor fabrication technologies continue to advance, the number of transistors in integrated circuits (ICs) has steadily increased. Initially, ICs contained only tens of transistors, but as technology progressed, ICs integrating hundreds of thousands of transistors enabled the realization of 3D animation. ICs with millions of transistors allowed computers to enter households, and today, ICs with hundreds of billions or even trillions of transistors enable digital technology to connect the entire world, profoundly impacting people’s lives.

Over the past 65 years, semiconductor fabrication processes have rapidly evolved, driven by Moore’s Law, gradually reshaping society. However, in recent years, semiconductor processes have approached physical limits, and the failure of Moore’s Law has been a topic of concern. In response, 3D IC stacking and heterogeneous integration technologies have emerged as promising solutions.

3D Stacking Trends

With the rapid development of applications such as AI, AR/VR, and 8K, a significant demand for computation is expected to continue, particularly driving parallel computing systems capable of handling vast amounts of data in a short time. As semiconductor processes slow down, 3D packaging has become an effective means to extend Moore’s Law and enhance IC computing performance.

3D packaging technology offers numerous advantages over traditional 2D packaging. It enables size reduction, with silicon interposer efficiency exceeding 100%, improved connectivity, reduced parasitic effects, lower power consumption, lower latency, and higher operating frequencies. These advantages, along with various benefits of 3D integration and interconnection technologies, make 3D packaging a development direction pursued by major players in the industry.

imec’s Vision for 3D Technology

In the field of 3D stacking technology, imec (imec, the Belgian Interuniversity Microelectronics Centre) defines four categories of 3D integration solutions: 3D-SIP, 3D-SIC, 3D-SOC, and 3D-IC, each requiring different process solutions and 3D integration techniques. Eric Beyne, VP R&D, Director 3D System Integration Program at imec specifically notes that concerning 3D interconnection technology, the scope of 3D interconnection will extend from stack packaging below 1 millimeter (mm), such as Package-on-Package (POP), to below 100 nanometers (nm) with true 3D ICs using transistor stacking, surpassing an interconnect density of 108/mm².

imec identifies three key elements in 3D integration technology: Through-Silicon Via (TSV), die-to-die and die-to-wafer stacking and interconnection, and wafer-to-wafer bonding technology. Beyne points out that TSV miniaturization technology continues to evolve. However, regarding “interconnect gaps,” as TSVs further shrink, microbump technology may struggle to meet higher interconnection demands, making cu-cu hybrid bonding technology a focus of development.

▲The image shows imec’s 3D interconnect technology roadmap, illustrating that as packaging technology continues to advance, node sizes shrink, and density further increases in 3D packaging. (Source：ISSCC 2021)

3D-SIP

System-in-Package (SIP), a form of system-level packaging, connects multiple chips that undergo different fabrication processes and preliminary packaging using heterogeneous integration techniques, integrating them within the same packaging shell. 3D-SIP involves vertically stacking multiple SIP chips, including packaging interconnects, fan-out wafer-level packaging, and solder ball bonding.

▲The image on the left is a schematic diagram of 3D-SIP packaging, where the connection points on both sides of the PCB board link the chips that have undergone initial packaging from top to bottom. The image on the right is an actual product illustration. (Source：TrendTorce (Left)，ISSCC 2021(Right))

Currently, the connection pitch in existing solutions is approximately 400 micrometers (µm). imec’s research aims to increase the interconnectivity of such SIPs by 100 times, reducing connection pitch to 40 µm. Common applications of 3D-SIP packaging include RF FEMs, TWS Barbuds SoCs.

3D-SIC

The second category, 3D-SIC (Stacking IC), involves the stacking of individual chips on top of each other. 3D-SIC is achieved by stacking chips on an interposer or wafer, with the finished chips bonded to the top of the wafer. Chips are interconnected through TSVs and microbumps, with industry solutions achieving pitch sizes as small as 40 µm. The technology is applied to products like 3D-DRAM and logic chips, connected alongside optical I/O units on the interposer. Currently, 3D-SIC technology is widely used in High-Bandwidth Memory (HBM) manufacturing.

▲The image depicts a schematic diagram of 3D-SIC, which utilizes cu-cu hybrid bonding technology to connect the upper and lower layers of ICs. (Source:imec)

3D stacking packaging is leading the global semiconductor industry, and imec has outlined a development blueprint focused on reducing interconnection pitch and increasing contact density per unit area, positioning 3D stacking as a solution to continue Moore’s Law amid slowing semiconductor processes.

Explore More

• An In-Depth Explanation of Advanced Packaging Technology: CoWoS
• Intel and Samsung Join TSMC in Fierce Advanced Packaging Race
• Continuing Moore’s Law: Advanced Packaging Enters the 3D Stacked CPU/GPU Era
• Understanding Chiplets, SoC, and SiP: Why TSMC, Intel, Samsung Invest?

This article is from TechNews, a collaborative media partner of TrendForce.

(Photo credit: TSMC )

Source to UDN, the DRAM market has been buzzing with positive developments lately, and may get a chance to see an upturn by the end of the year. Among the key factors driving this optimism is the DDR5 specification DRAM, which is poised to capitalize on opportunities in AI servers and laptops next year, gradually increasing demand.

After more than a year of corrections, the DRAM market is finally showing signs of improvement. Major DRAM manufacturers like Samsung and SK Hynix are still reducing production capacity, but their focus is primarily on DDR4 specification DRAM. Industry sources suggest that Samsung, in response to the growing demand for DDR5 DRAM, is set to significantly ramp up DDR5 production in the fourth quarter of this year, anticipating strong order demand next year.

In fact, such as Intel and AMD are planning to introduce new platforms next year that will support DDR5 specification DRAM, indicating a gradual decline in DDR4 demand. Beyond the consumer market, the server market is expected to experience a substantial surge in DDR5 demand, driven by the imminent launch of Intel’s fifth-generation server platform, Emerald Rapids, which fully supports DDR5. As AI server demand gains momentum, DDR5 demand is poised to enter a high-growth phase.

(Source: https://money.udn.com/money/story/5612/7488629 ; Image credit: Micron)

The Silicon Photonics topic is heating up as major companies race to address the data transfer speed between chips. Intel’s Silicon Photonics project has a leading advantage, while TSMC is collaborating with major customers Nvidia and Broadcom, investing 200 research and development personnel. They aim to complete the project in the second half of 2024, with production set to begin in 2025.

According to Taiwan’s Commercial Times, Luo Huaijia, the Executive Director of the Photonics Industry and Technology Development Association (PIDA) in Taiwan, stated that silicon photonics technology has always been a crucial focus in the field of photonics. Photonics products are evolving towards being compact, lightweight, energy-efficient, and power-saving.

Among Taiwan’s semiconductor fabs, TSMC stands out with its COUPE, which provides heterogeneous integration of photonic integrated circuits (PIC) and electronic integrated circuits (EIC), reducing energy consumption by 40%. TSMC is rumored to deploy a 200-person R&D team, collaborating with international major clients for joint development. Consequently, following the completion of its Hsinchu plant, TSMC invested NT$90 billion in constructing a new packaging plant in Tongluo, Miaoli, recognizing the significant demand and potential in heterogeneous integration.

Luo Huaijia pointed out that silicon photonics uses semiconductor technology to create a platform with optical properties, with the goal of integrating light and telecommunications signals. This involves packaging traditional optical components, including optical waveguides, light-emitting elements, and transceiver modules, together, thus also involving heterogeneous packaging.

As early as 2002, Intel publicly conducted research in the field of “Silicon Photonics,” but at that time, the data volume could be handled with copper wire transmission. Luo Huaijia believes that with the exponential increase in AI computing power, data processing will start in the gigabyte range, prompting companies to invest heavily in development.

Luo Huaijia analyzed that currently, GlobalFoundries is likely the first company to provide wafer foundry services for manufacturing optical fiber transceivers, using FD-SOI technology integration solutions. Intel also currently offers a 400Gb/s optical fiber transceiver solution. In addition to their own ASICs or FPGAs, this technology is applied to Switch ICs. Intel even plans to expand its silicon photonics solution into the automotive market, using it in Mobileye’s optical radar by 2025.

Explore More

• What Is ‘Silicon Photonics’? Why Intel, TSMC, NVIDIA, Apple Are Investing
• Silicon Photonics Will Become Key to Semiconductor Future Development

(Photo credit: ITRI)

As the United States intensifies its chip embargo against China, the Chinese Academy of Engineering (CAE) has released an annual report for technological development. This report serves as a strategic guide to navigate the embargo and promote autonomous technological growth comprehensively.
…