In the latest financial report and guidance released on the 20th, U.S. memory chip giant Micron outperformed analysts’ expectations for both the last quarter and the current quarter. CEO Sanjay Mehrotra believes that product pricing will rebound next year, with the upward trend continuing until 2025, as Micron aims to return to a path of operational innovation and reach new record levels by 2025, according to The Economic Daily.

Mehrotra anticipates a price recovery in memory prices next year, and rise further in 2025. He reiterated in a statement that 2024 will be a year of recovery for the memory industry setting the stage for record results in 2025.

Micron expects the supply of PC, mobile devices, and other chips to approach normal levels in the first half of next year. Despite two consecutive years of declining PC shipments, Micron forecasts low to mid-single-digit percentage growth in 2024, with signs of a recovery in smartphone demand.

TrendForce also anticipates that the upward momentum in DRAM products is expected to continue until 2025.

The reason behind this is the continuous benefit to the DRAM market from the increasing penetration of premium products such as HBM, DDR5 and LPDDR5. This is expected to have a positive impact on the overall memory prices.

Simultaneously, TrendForce believes that 2025 will witness the emergence of more edge AI applications, such as AI on smartphones or PCs. This is expected to result in an increase in DRAM capacity, becoming the driving force for the next wave of growth in DRAM demand.

(Image: Micron)

One of the shareholders of Shanghai Micro Electronics Equipment Group (SMEE), Zhangjiang Group, recently posted on WeChat, claiming that SMEE had successfully developed a 28nm lithography machine. However, the mentioned text was deleted shortly thereafter.

According to reports from Bloomberg and HK01, recently, Zhangjiang Group posted on the WeChat public account “Hello Zhangjiang,” stating, “As the only domestic enterprise mastering photolithography machine technology, SMEE has successfully developed a 28nm lithography machine.”

However, shortly afterward, the text was modified to “As the only domestic enterprise mastering photolithography machine technology, SMEE is committed to developing advanced lithography machines.”

Reportedly, the lithography machine developed by SMEE is named SSA/800-10W, representing a significant breakthrough for the company.

Tom’s Hardware indicated that SMEE’s successful development of 28nm lithography machine signifies ‘a major leap in China’s quest to close the technological gap in the global chip industry’. However, it is currently unclear when SMEE will be able to mass-produce these devices.

Additionally, the deletion of the information raises questions about the success of mass production once again.

The report further indicates that TSMC has been using 28nm process since 2011, and SMIC adopted it in 2015. Both companies chose equipment from ASML to manufacture chips.

Last year, the U.S. Department of Commerce blacklisted SMEE. Since then, SMEE has been seen as China’s best hope for pursuing the development of advanced manufacturing processes.

The existing SSA600 series from the company can utilize 90nm, 110nm, and 280nm process. The latest equipment from the company is expected to narrow the gap with ASML, potentially reducing the initial lag of at least 20 years.

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(Photo credit: SMEE)

Following TSMC’s first plant built in Japan’s Kumamoto Prefecture, Samsung has also chosen Yokohama as the location for its new facility in Japan.

According to Japanese media NHK’s report, South Korean Samsung Electronics has decided the establishment of a new semiconductor research and development center in Yokohama, Japan. with a total investment of JPY 40 billion (approximately USD 278 million).

The Japanese government is set to provide half of the total subsidy for this investment. The project is expected to commence next year and will focus on the research and development of advanced packaging.

Additionally, Samsung plans to hire around 100 local engineers in Japan and is cautiously evaluating the possibility of collaboration with Japanese research organizations.

NHK, citing sources, reported that Japanese Prime Minister Kishida Fumio plans to announce this expanded investment in Japan soon.

Given the continuous competition between China and the United States in the semiconductor sector, the calls for strengthening the domestic semiconductor supply chain in Japan have grown louder.

Consequently, the Japanese government has been encouraging foreign chipmakers to establish a presence in Japan, aiming to reinforce domestic supply chains.

As of May this year, Kishida Fumio met with seven semiconductor giants, including Intel, Samsung, Micron, and TSMC. The meeting demonstrated a commitment to revitalize Japan’s semiconductor industry. At that time, rumors about Japan providing subsidies to Samsung already existed, sparking market discussions.

(Photo credit: Samsung)

Intel CEO Pat Gelsinger has discussed around Intel’s process status, comparisons with TSMC in a recent interview. According to Barron’s report, Gelsinger mentioned in the interview that Intel’s 18A process and TSMC’s N2 process seem comparable, with no significant advantage for either of them.

However, Gelsinger claimed that, ‘But the backside power delivery, everybody says Intel, score.’ He further stated, ‘it gives better area efficiency for silicon, which means lower cost. It gives better power delivery, which means higher performance.’

Gelsinger mentioned that good transistor and great power delivery make 18A a little bit ahead of N2. Besides, TSMC has given a very high-cost envelope, where Intel can fit underneath to be margin accretive.

In fact, not only TSMC and Intel, but also including Samsung, the three semiconductor manufacturing giants are actively positioning themselves in the increasingly competitive field of advanced process technology.

At the recent IEEE International Electron Devices Meeting (IEDM), Intel, TSMC, and Samsung each showcased their CFET (Complementary FET) transistor solutions. The stacked CFET transistor architecture involves stacking two types of transistor -nFETs and pFETs- together, aiming to replace Gate-All-Around (GAA) and become the next-generation transistor design for doubling density.

As reported by IEEE Spectrum, Intel was the first foundry to showcase the CFET solution, publicly unveiling an early version back in 2020. During the conference, Intel introduced one of the simplest circuits manufactured with CFET, focusing on improvements for an inverter.

The CMOS inverter sends the same input voltage to the gates of two-transistor stacked together, generating an output that is logically opposite to the input, and the inverter is completed on a single fin.

Intel also improved the CFET stack’s electrical characteristics by increasing the number of nanosheets per device from two to three, decreasing the separation between the two devices from 50 nm to 30 nm.

According to the current progress, experts, as indicated by IEEE Spectrum, anticipate that the commercialization of CFET technology on a large scale will likely take another 7 to 10 years from now. Before reaching that stage, there are still many preparatory tasks that need to be completed.

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(Photo credit: Intel)

According to a report by TechNews, TSMC’s Arizona-based Fab21, currently in the intensive equipment installation phase, has initiated the construction of a small-scale trial production line. With a small amount of equipment expected from multiple supply chain by the end of 2023, industry sources suggest that Fab21 is planning to commence trial production in the first quarter of 2024.

The reason behind TSMC’s anticipated trial production in the first quarter of 2024 stems from orders from its U.S. clients. Market reports indicate that among Fab21’s U.S. clients, in addition to major players like , NVIDIA CEO Jensen Huang has not ruled out placing orders with Fab21. Furthermore, there are indications that Intel, planning to outsource core computing to TSMC’s N3B process, is likely to place orders to Fab21 in the near future.

However, due to cost considerations, despite the commencement of a small-scale trial production line, the initial capacity increase for Fab21’s 4-nanometer process will not accelerate. This situation is expected to persist into the subsequent second phase of the 3-nanometer production line.

Looking back at TSMC’s progress in Arizona, the company announced the construction of the 12-inch wafer Fab21 in Arizona back in 2020, anticipating the commencement of formal equipment installation in the first quarter of 2024 and official mass production before the end of 2024. The initial phase of Fab21 will produce on the 5-nanometer process, with a monthly production capacity of 20,000 wafers.

TSMC later upgraded the initial processs from 5-nanometer to 4-nanometer. However, due to a shortage of skilled installation workers in the region, TSMC postponed the mass production start date to 2025.

In addition, the second phase of the project is currently slated for mass production in 2026, introducing the 3-nanometer process. The total investment for both phases amounts to $40 billion.

Industry sources also acknowledge that Fab21’s manufacturing costs are high, and its capacity cannot compete with TSMC’s fab in Taiwan, making U.S. client orders primarily a response to U.S. government requirements, with the majority of production still centered in Taiwan.

(Image: TSMC)