Market reports suggest Nvidia’s new product release cycle has shortened from two to a year, sparking intense competition among major memory companies in the realm of next-gen High Bandwidth Memory (HBM) technology. Samsung, SK Hynix, and Micron are fervently competing, with SK Hynix currently holding the dominant position in the HBM market. However, Micron and Samsung are strategically positioned, poised for a potential overtake, reported by TechNews.

Current Status of the HBM Industry

SK Hynix made a breakthrough in 2013 by successfully developing and mass-producing HBM using the Through Silicon Via (TSV) architecture. In 2019, they achieved success with HBM2E, maintaining the overwhelming advantage in the HBM market. According to the latest research from TrendForce, Nvidia plan to partner with more HBM suppliers. Samsung, as one of the suppliers, its HBM3 (24GB) is anticipated to complete verification with NVIDIA by December this year.

Regarding HBM3e progress, Micron, SK Hynix, and Samsung provided 8-layer (24GB) Nvidia samples in July, August, and October, respectively, with the fastest verification expected by year-end. All three major players anticipate completing verification in the first quarter of 2024.

As for HBM4, the earliest launch is expected in 2026, with a stack increase to 16 layers from the existing 12 layers. The memory stack will likely adopt a 2048-bit memory stack connection interface, driving demand for the new “Hybrid Bonding” stacking method. The 12-layer HBM4 product is set to launch in 2026, followed by the 16-layer product expected in 2027.

Navigating HBM4, the New Technologies and Roadmaps of Memory Industry Leaders

SK Hynix

According to reports from Business Korea, SK Hynix is preparing to adopt “2.5D Fan-Out” packaging for the next-generation HBM technology. This move aims to enhance performance and reduce packaging costs. This technology, not previously used in the memory industry but common in advanced semiconductor manufacturing, is seen as having the potential to “completely change the semiconductor and foundry industry.” SK Hynix plans to unveil research results using this packaging method as early as next year.

The 2.5D Fan-Out packaging technique involves arranging two DRAM horizontally and assembling them similar to regular chips. The absence of a substrate beneath the chips allows for thinner chips, significantly reducing the thickness when installed in IT equipment. Simultaneously, this technique bypasses the Through Silicon Via (TSV) process, providing more Input/Output (I/O) options and lowering costs. 

According to their previous plan, SK Hynix aims to mass-produce the sixth-generation HBM (HBM4) as early as 2026. The company is also actively researching “Hybrid Bonding” technology, likely to be applied to HBM4 products.

Currently, HBM stacks are placed on the interposer next to or GPUs and are connected to their interposer. While SK Hynix’s new goal is to eliminate the interposer completely, placing HBM4 directly on GPUs from companies like Nvidia and AMD, with TSMC as the preferred foundry.

Samsung

Samsung is researching the application of photonics in HBM technology’s interposer layer, aiming to address challenges related to heat and transistor density. Yan Li, Principal Engineer in Samsung’s advanced packaging team, shared insights at the OCP Global Summit in October 2023.

(Image: Samsung)

According to Samsung, The industry has made significant strides in integrating photonics with HBM through two main approaches. One involves placing a photonics interposer between the bottom packaging layer and the top layer containing GPU and HBM, acting as a communication layer. However, this method is costly, requiring an interposer and photon I/O for logic chips and HBM.

(Image: Samsung)

The alternative approach separates the HBM memory module from packaging, directly connecting it to the processor using photonics. Rather than dealing with the complexity of packaging, a more efficient approach is to separate the HBM memory module from the chip itself and connect it to the logic IC using photonics technology. This approach not only simplifies the manufacturing and packaging costs for HBM and logic ICs but also eliminates the need for internal digital-to-optical conversions in the circuitry. However, careful attention is required to address heat dissipation.

Micron

As reported by Tom’s Hardware, Micron’s 8-layer HBM3e (24GB) is expected to launch in early 2024, contributing to improved AI training and inference performance. The 12-layer HBM3e (36GB) chip is expected to debut in 2025.

Micron is working on HBM4 and HBM4e along with other companies. The required bandwidth is expected to exceed 1.5 TB/s. Micron anticipates launching 12-layer and 16-layer HBM4 with capacities of 36GB to 48GB between 2026 and 2027. After 2028, HBM4E will be introduced, pushing the maximum bandwidth beyond 2+ TB/s and increasing stack capacity to 48GB to 64GB.

Micron is taking a different approach from Samsung and SK Hynix by not integrating HBM and logic chips into a single die, suggested by Chinese media Semiconductor Industry Observation. This difference in strategy may lead to distinct technical paths, and Micron might advise Nvidia, Intel, AMD that relying solely on the same company’s chip carries greater risks.

(Image: Micron)

TSMC Aids Memory Stacking       

Currently, TSMC 3DFabric Alliance closely collaborates with major memory partners, including Micron, Samsung, and SK Hynix. This collaboration ensures the rapid growth of HBM3 and HBM3e, as well as the packaging of 12-layer HBM3/HBM3e, by providing more memory capacity to promote the development of generative AI.

(Image: TSMC)

(Image: SK Hynix)

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The investment momentum of China’s Big Fund Phase II shows no signs of slowing down, with its latest investment directed at Shanghai Huali Microelectronics Co., Ltd. (HLMC), a subsidiary of Huahong Group.

According to Sina Finance’s report, this substantial investment of up to USD 1 billion will support HLMC in continuous development of advanced process technologies and enhancing its manufacturing capabilities.

Given industry reports from as early as 2020 suggesting HLMC has progressed to the 14nm process, this investment from the Big Fund II signifies China’s commitment to even more advanced processes below 10nm in pursuit of semiconductor self-sufficiency.

Recently, Huahong Corporation announced that, to accelerate the research and development as well as mass production of the 40nm featured IC process on the 12-inch wafer production line in Wuxi, Jiangsu Province, jointly established by its wholly-owned subsidiary Huahong Hongli and other joint venture partners, Huahong Hongli signed a “Technology Development Agreement” with HLMC on December 1, 2023.

The agreement stipulates that HLMC will provide Huahong Hongli with 40nm logic fundamentals and related process technology, along with corresponding technical services, consultation, and support.

In contrast to Semiconductor Manufacturing International Corp. (SMIC), historically positioned as China’s leading foundry to compete with TSMC, HLMC has maintained a more discreet profile.

Officially capable of manufacturing chips on 22nm- and 28nm-class fabrication technologies, rumors circulated in the market as early as 2020 that HLMC could produce chips on a 14nm FinFET process nodes using deep ultraviolet (DUV).

Moreover, leveraging DUV multi-patterning methods could potentially drive production for advanced processes below 10nm, contributing to China’s pursuit of semiconductor self-sufficiency.

HLMC increased its registered capital from approximately CNY 22 billion to around CNY 28.4 billion, with Big Fund Phase II holding a stake exceeding 10%. This data indicates Big Fund Phase II’s confidence in HLMC’s development, providing substantial financial support to bolster its progress in semiconductor processes.

The investment direction of Big Fund Phase II differs from that of Big Fund Phase I, which primarily focusing on key industries such as chip manufacturing. It is more diversified, spanning multiple areas, including wafer manufacturing, integrated circuit design tools, chip design, packaging testing, equipment, components, materials, and applications.

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(Photo credit: Hua Hong Group)

Memory prices continue to rise, with the world’s top five memory chip manufacturers, including Western Digital (WDC), notifying their distributors and consumer customers on December 5th that they will shorten the quoting period for their two major products – HDD and NAND Flash memory. Instead, they will adopt a pricing strategy of periodic adjustments to cope with the rapidly changing storage market.

Despite the traditional peak season of the tech industry nearing its end, memory industry insiders indicate that the off-season is not slack. WDC predicts a lively scenario of “weekly increases” in quotations, potentially prompting OEM customers to place orders earlier.

This trend is advantageous for raising both spot prices and contract prices for memory in the first quarter of the coming year.

The content of the letter sent by WDC to its channel customers is as follows:

“HDD – We will continue to review pricing on a weekly basis, with increases expected through the first half of next year.

Flash – We anticipate periodic price increases over the next few quarters, with the cumulative increase likely surpassing 55% of current levels.”

We have aligned our production capacity to the current demand environment, so our ability to respond to unplanned demand and orders is limited. Please ensure any changes to your orders are communicated as early as possible. Anticipate extended lead times for any unplanned demand.

According to industry sources in the memory sector, the letter from WDC primarily serves as a notice to OEM customers related to its two major product lines, HDD and NAND Flash. Due to major international memory manufacturers actively reducing production and controlling capacity to maintain prices, this has led to a significant rebound in NAND prices.

In recent times, both spot and contract prices have shown an upward trend, and HDD prices have been on the rise since the second half of this year.

Based on TrendForce’s data, WDC has benefited from the recovery in demand in the consumer electronics sector. The increase in NAND bit shipments in the third quarter has driven revenue upward, reaching USD 1.556 billion in the third quarter, showing a 13% quarterly increase.

The original plan for WDC was to merge with Japanese counterpart Kioxia, but after negotiations fell through in October, it was announced that WDC would be split into two publicly listed companies.

According to foreign reports, WDC has previously issued a statement announcing the spin-off of its flash memory business. Reportedly, the separated business will focus on memory for computers, devices, and portable hard drives, while the HDD business will concentrate on selling large-capacity memory to cloud data centers.

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(Photo credit: WDC)

Samsung, the Korean tech giant, has unveiled SAINT technology to counter TSMC’s advanced CoWoS packaging, aiming to benefit from the surging AI market. Market reports reveal that Samsung is strategically procuring a substantial amount of 2.5D packaging equipment, indicating a keen awareness of the soaring demand from AI chip companies like NVIDIA, reported by Korean media The Elec.

Samsung has acquired 16 sets of packaging equipment from the Japanese company Shinkawa. Currently, 7 sets have been received, with the possibility of additional orders based on future requirements. Samsung’s objective is to demonstrate its prowess in packaging and HBM technologies, seeking recognition and partnership with NVIDIA. As the limitations in NVIDIA’s current supply chain, especially due to insufficient CoWoS advanced packaging capacity in TSMC, Samsung emerges as a promising alternative for diverse supply chain.

On the other hand, NVIDIA’s ambitious goal of achieving USD 300 billion in AI sector revenue by 2027 requires a reliable supply chain, as per reported by TechNews. To this end, Samsung is poised to supply its next-gen GPU, Blackwell, featuring HBM3 and 2.5D packaging. This move aligns with NVIDIA’s strategy to diversify its supply chain away from existing providers like TSMC.

For Samsung, this collaboration presents a significant opportunity to enter the thriving AI market. Success in this venture could not only bolster the financial performance of Samsung’s memory and advanced packaging divisions but also open doors to orders from players like AMD and Tesla. However, the key lies in how effectively Samsung meets the formidable market demand, particularly in semiconductor production, advanced packaging, and memory technology.

(Image: Samsung)

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As reported earlier, the global provider of outsourced semiconductor packaging and test services, Amkor, has been set to establish its presence in Arizona, USA, providing advanced packaging services for Apple chips manufactured by TSMC.

According to reports from South Korean media, the alliance formed among Apple, TSMC, and Amkor may pose a significant challenge to the South Korean semiconductor giant, Samsung Electronics, potentially creating competition for contracts and drawing close attention from the industry.

Amkor released a statement on November 30, announcing the establishment of the new facility in Peoria, northwest of Phoenix, Arizona. The construction is expected to commence in the second half of 2024, focusing primarily on advanced packaging requirements for high-end chips related to IoT, automotive electronics, 5G, artificial intelligence (AI), and high-performance computing (HPC). The facility has already secured orders from major players, with Apple being its first and largest customer.

Coincidentally, TSMC is also in the process of constructing an advanced process semiconductor wafer facility in Phoenix. 

TrendForce’s research has indicated that the current maximum capacity plan for TSMC’s Arizona plant is around 50,000, with 20-30,000 allocated for 4nm and 3nm each. It is anticipated that the expansion to this scale will only occur after 2027. This capacity is expected to cater to a limited number of domestic customers in the United States who require fully American-made semiconductor products.

Business Korea’s report also suggests that the alliance formed among Apple, TSMC, and Amkor may impact Samsung. Samsung’s second wafer facility in the U.S., located in Taylor City, Texas, is anticipated to start production in the second half of 2024, setting the stage for potential chip procurement battles with TSMC.

Speculations have arisen about Samsung possibly establishing a testing and packaging facility in Taylor City, following the strategy of strengthening vertical integration to enhance competitiveness and gain an advantage in chip procurement.

In November of this year, Samsung unveiled a new strategy called “GDP,” focusing on Gate-All-Around (GAA) transistor technology, DRAM, and 3.5D advanced packaging. The company has pledged to achieve a goal where more than half of its wafer foundry revenue comes from AI chip orders within five years.

(Photo credit: TSMC)

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