As applications like AIGC, 8K, AR/MR, and others continue to develop, 3D IC stacking and heterogeneous integration of chiplet have become the primary solutions to meet future high-performance computing demands and extend Moore’s Law.

Major companies like TSMC and Intel have been expanding their investments in heterogeneous integration manufacturing and related research and development in recent years. Additionally, leading EDA company Cadence has taken the industry lead by introducing the “Integrity 3D-IC” platform, an integrated solution for design planning, realization, and system analysis simulation tools, marking a significant step towards 3D chip stacking.

Differences between 2.5D and 3D Packaging

The main difference between 2.5D and 3D packaging technologies lies in the stacking method. 2.5D packaging involves stacking chips one by one on an interposer or connecting them through silicon bridges, primarily used for assembling logic processing chips and high-bandwidth memory. On the other hand, 3D packaging is a technology that vertically stacks chips, mainly targeting high-performance logic chips and SoC manufacturing.

CPU and HBM Stacking Demands

With the rapid development of applications like AIGC, AR/VR, and 8K, it is expected that a significant amount of computational demand will arise, particularly driving the need for parallel computing systems capable of processing big data in a short time. To overcome the bandwidth limitations of DDR SDRAM and further enhance parallel computing performance, the industry has been increasingly adopting High-Bandwidth Memory (HBM). This trend has led to a shift from the traditional “CPU + memory (such as DDR4)” architecture to the “Chip + HBM stacking” 2.5D architecture. With continuous growth in computational demand, the future may see the integration of CPU, GPU, or SoC through 3D stacking.

3D Stacking with HBM Prevails, but CPU Stacking Lags Behind

HBM was introduced in 2013 as a 3D stacked architecture for high-performance SDRAM. Over time, the stacking of multiple layers of HBM has become widespread in packaging, while the stacking of CPUs/GPUs has not seen significant progress.

The main reasons for this disparity can be attributed to three factors: 1. Thermal conduction, 2. Thermal stress, and 3. IC design. First, 3D stacking has historically performed poorly in terms of thermal conduction, which is why it is primarily used in memory stacking, as memory operations generate much less heat than logic operations. As a result, the thermal conduction issues faced by current memory stacking products can be largely disregarded.

Second, thermal stress issues arise from the mismatch in coefficients of thermal expansion (CTE) between materials and the introduction of stress from thinning the chips and introducing metal layers. The complex stress distribution in stacked structures has a significant negative impact on product reliability.

Finally, IC design challenges from a lack of EDA tools, as traditional CAD tools are inadequate for handling 3D design rules. Developers must create their own tools to address process requirements, and the complex design of 3D packaging further increases the design, manufacturing, and testing costs.

How EDA Companies Offer Solutions

Cadence, during the LIVE Taiwan 2023 user annual conference, highlighted its years of effort in developing solutions. They have introduced tools like the Clarity 3D solver, Celsius thermal solver, and Sigrity Signal and Power Integrity, which can address thermal conduction and thermal stress simulation issues. When combined with Cadence’s comprehensive EDA tools, these offerings contribute to the growth of the “Integrity 3D-IC” platform, aiding in the development of 3D IC design.

“3D IC” represents a critical design trend in semiconductor development. However, it presents greater challenges and complexity than other projects. In addition to the challenges in Logic IC design, there is a need for analog and multi-physics simulations. Therefore, cross-platform design tools are indispensable. The tools provided by EDA leader Cadence are expected to strengthen the 3D IC design tool platform, reducing the technological barriers for stacking CPU, GPU, or SoC to enhance chip computing performance.

This article is from TechNews, a collaborative media partner of TrendForce.

(Photo credit: TSMC)

In its FY2Q24 earnings report for 2023, NVIDIA disclosed that the U.S. government had imposed controls on its AI chips destined for the Middle East. However, on August 31, 2023, the U.S. Department of Commerce stated that they had “not prohibited the sale of chips to the Middle East” and declined to comment on whether new requirements had been imposed on specific U.S. companies. Both NVIDIA and AMD have not responded to this issue.

TrendForce’s analysis:

• Close ties between Middle Eastern countries and China raise U.S. concerns:

In NVIDIA’s FY2Q24 earnings report, it mentioned, “During the second quarter of fiscal year 2024, the USG informed us of an additional licensing requirement for a subset of A100 and H100 products destined to certain customers and other regions, including some countries in the Middle East.” It is speculated that the U.S. is trying to prevent high-speed AI chips from flowing into the Chinese market via the Middle East. This has led to controls on the export of AI chips to the Middle East.

Since August 2022, the U.S. has imposed controls on NVIDIA A100, H100, AMD MI100, MI200, and other AI-related GPUs, restricting the export of AI chips with bidirectional transfer rates exceeding 600GB/s to China. Saudi Arabia had already signed a strategic partnership with China in 2022 for cooperation in the digital economy sector, including AI, advanced computing, and quantum computing technologies. Additionally, the United Arab Emirates has expressed interest in AI cooperation with China. There have been recent reports of Saudi Arabia heavily acquiring NVIDIA’s AI chips, which has raised concerns in the U.S.

• Huawei is expected to release AI chips comparable to NVIDIA A100 in the second half of 2024; competition is yet to be observed:

Affected by U.S. sanctions, Chinese companies are vigorously developing AI chips. iFlytek is planning to launch a new general-purpose LLM (Large Language Model) in October 2023, and the AI chip Ascend 910B, co-developed with Huawei, is expected to hit the market in the second half of 2024, with performance claimed to rival that of NVIDIA A100. In fact, Huawei had already introduced the Ascend 910, which matched the performance of NVIDIA’s V100, in 2019. Considering Huawei’s Kirin 9000s, featured in the flagship smartphone Mate 60 Pro released in August 2023, it is highly likely that Huawei can produce products with performance comparable to A100.

However, it’s important to note that the A100 was already announced by NVIDIA in 2020. This means that even if Huawei successfully launches a new AI chip, it will already be four years behind NVIDIA. Given the expected 7nm process for Huawei’s Ascend 910B and NVIDIA’s plan to release the 3nm process-based Blackwell architecture GPU B100 in the second half of 2024, Huawei will also lag behind by two generations in chip fabrication technology. With the parameters of LLM doubling annually, the competitiveness of Huawei’s new AI chip remains to be observed.

• China remains NVIDIA’s dominion in the short term:

Despite the active development of AI chips by Chinese IC design house, NVIDIA’s AI chips remain the preferred choice for training LLM models among Chinese cloud companies. Looking at the revenue performance of the leading Chinese AI chip company, Cambricon, its revenue for the first half of 2023 was only CNY 114 million, a YoY decrease of 34%. While being added to the U.S. Entity List was a major reason for the revenue decline, NVIDIA’s dominance in the vast Chinese AI market is also a contributing factor. It is estimated that NVIDIA’s market share in the Chinese GPU market for AI training exceeded 95% in the first half of 2023. In fact, in the second quarter of 2023, the China market accounted for 20-25% of NVIDIA’s Data Center segment revenue.

The main reason for this is that the Chinese AI ecosystem is still quite fragmented and challenging to compete with NVIDIA’s CUDA ecosystem. Therefore, Chinese companies are actively engaged in software development. However, building a sufficiently attractive ecosystem to lure Chinese CSPs in the short term remains quite challenging. Consequently, it is expected that NVIDIA will continue to dominate the Chinese market for the next 2-3 years.

(Photo credit: NVIDIA)

According to Taiwan’s Economic Daily, TSMC Chairman Mark Liu stated on 9/6 that semiconductor technology development “has reached the exit of the tunnel, and there are more possibilities beyond the tunnel; we are no longer bound by the tunnel.”

Regarding TSMC’s progress in establishing a factory in the United States, Liu mentioned that this project has received support from the local government and has made significant progress in recent months. He added, “We will certainly make it very successful.”

As for the recent shortage of chips caused by generative AI, Liu noted that it is not due to TSMC’s manufacturing capacity but rather the sudden threefold increase in CoWoS (Chip-on-Wafer-on-Substrate) demand. TSMC will continue to support the demand in the short term but cannot immediately ramp up production. Liu estimated that TSMC’s capacity will catch up with customer demand in about a year and a half, considering the capacity bottleneck as a short-term phenomenon.

Regarding SoftBank Group’s subsidiary, Arm, planning an initial public offering (IPO) to raise funds, Liu also revealed that they are evaluating whether to become an investor in Arm, with a decision expected in the next one or two weeks. He emphasized Arm’s importance within the semiconductor ecosystem, expressing TSMC’s desire for a successful Arm IPO.

Huawei’s official website unexpectedly unveiled its latest flagship smartphone, the Mate 60 Pro, on August 29, 2023, followed by the release of the Mate 60 the next day. The Mate 60 Pro’s performance, powered by the Kirin 9000S SoC, has garnered significant attention in the market.

TrendForce’s Insights:

• Kirin 9000S Offers Comparable Computing Power to 2021 Flagships, But Energy Efficiency May Lag

According to benchmark test results from the Geekbench Browser, a product known as Huawei LNA-AL00, believed to be housing the Kirin 9000S, first appeared in test data on March 30, 2023, and has been continually updated since. The test results for Huawei LNA-AL00 during this period fall into two ranges. One range is roughly equivalent to the Qualcomm Snapdragon 8+ Gen 1, while the other is on par with the Qualcomm Snapdragon 888. This suggests potential variations in Kirin 9000S versions.

Further analysis of the Kirin 9000S reveals that its CPU architecture maintains the 1+3+4 configuration of the Kirin 9000 but operates at slightly lower clock speeds, with a difference of approximately 10-20%. The GPU is Huawei’s in-house Maleoon 910. However, in comparison to the Kirin 9000, which employs TSMC’s 5nm process, the Kirin 9000S has a larger chip size, roughly 30% larger. Additionally, the presence of a large Vapor Chamber beneath the Mate 60 Pro’s screen indicates that the Kirin 9000S may have higher energy consumption, reflecting the use of a less advanced process than TSMC’s 7nm. Overall, Kirin 9000S is expected to offer computing performance similar to mainstream flagships from 2021-2022, but its energy efficiency might align with levels seen in 2019-2020.

• Maintaining Performance Gap with Other Flagship SoCs Will Be a Key Challenge for Huawei and SMIC

Based on available information, Kirin 9000S is likely produced by SMIC. Currently, SMIC’s advanced process nodes include 14nm, N+1, and N+2. Since SMIC has indicated that the N+1 process is not equivalent to 7nm, it is speculated to fall between 10-8nm. To produce Kirin 9000S, it would need to utilize an N+2 process closer to 7nm, which is currently the most suitable process node for domestic wafer foundries in China.

Kirin 9000S undoubtedly represents the pinnacle of China’s domestic IC design and manufacturing capabilities. In terms of computing performance, it lags only 2-3 years behind Qualcomm and MediaTek’s upcoming flagship SoCs set to be launched in the second half of 2023. However, without access to EUV equipment, SMIC faces significant challenges in developing processes below 7nm, and even achieving mass production at 5nm is not a short-term goal.

As Qualcomm and MediaTek advance their products to 4nm and below, the Kirin series will likely remain constrained by SMIC’s process technology, making it difficult to significantly increase clock speeds and reduce power consumption. This situation will lead to a gradual widening of the performance gap between the Kirin series and Snapdragon 8 Gen series, and the Dimensity series. As they grapple with the responsibility of technological advancement, maintaining a competitive performance gap for the Kirin series against other flagship SoCs will be a primary challenge for Huawei and SMIC moving forward.

(Photo credit: Huawei)

DRAM Spot Market
Compared with last week, transaction prices in the spot market have generally stopped falling, but there is no sustained upward momentum. Although suppliers and other spot sellers have been firm on prices and are unwilling to make further concessions, the overall transaction volume has continued to shrink because there has been no turnaround in the demand for end products. Further observations are needed to determine the trajectory of spot prices in the future. Nevertheless, TrendForce believes that suppliers will need to further expand the scale of their production cuts in 4Q23 in order to effectively reduce their existing inventories. The average spot price of mainstream chips (i.e., DDR4 1Gx8 2666MT/s) dropped by 0.07% from US$1.451 last week to US$1.450 this week.

NAND Flash Spot Market
Concluded prices have largely leveled to that of last week without dynamics for ongoing increment. Buyers, despite active stocking behaviors seen recently, are no longer following up on prices aggressively under the yet-to-be-improved level of actual end demand. Subsequent spot price trends will require further observation, though TrendForce believes that NAND Flash suppliers would be forced to expand production cuts during 4Q23 so as to further abate their existing inventory. 512Gb TLC wafer spots have risen by 0.63% this week, arriving at US$1.588.