According to South Korean media Chosun Biz’s report, the prices of all memory products, encompassing servers, mobile devices, and PCs, are on the rise. This trend, combined with the thriving development of the AI market, is expected to result in even higher profitability for High-Bandwidth Memory (HBM) than initially anticipated.

Major memory manufacturers Samsung and SK Hynix are beginning to emerge from a business downturn, leading to upward revisions in their financial outlook for the fourth quarter of 2023.

The report notes that the adjustments in Q4 financial outlook by Samsung and SK Hynix indicate a rapid increase in demand for HBM due to the thriving AI market. Additionally, the recovery of the largest sales item, DRAM, is contributing to better operational performance for both companies in the fourth quarter.

Market experts reveal that Samsung’s projected operating profit for Q4 is expected to be KRW 3.487 trillion, showing slight growth compared to the estimate from a week ago. As for SK Hynix, the expected loss in Q4 is KRW 294.4 billion, reflecting a convergence from the market estimate of KRW 335.3 billion a week earlier, despite remaining in a deficit.

In addition, Micron, the American company considered one of the three major global DRAM manufacturers along with South Korean companies Samsung and SK Hynix, has also revised its financial forecast for the first quarter of the 2024 fiscal year.

The initial estimate in November of USD 4.4 billion has been adjusted to USD 4.7 billion , while the expected Earnings per Share has been raised from USD -1.07 to USD -1.

Regarding trends in the memory industry, TrendForce indicated in a recent report that a key turning point in the third quarter for the NAND Flash market was Samsung’s decision to actively reduce production.

Previously, buyers maintained a low inventory and slow procurement strategy due to concerns about low visibility of end demand and worries about a lackluster market peak season. With the leading supply-side companies significantly reducing production, buyers, anticipating a significant reduction in supply, have shifted to a more positive procurement attitude. By the end of the third quarter, contract pricing for NAND Flash had shifted toward stabilization and even price increases.

TrendForce predicts that NAND Flash products will experience both increased volume and prices in the fourth quarter. The average selling price for all products is estimated to increase by 13%, and the overall revenue growth for the NAND Flash industry in the quarter is expected to exceed 20%.

Contrarily, in the case of DRAM, prices have been on a downward trend since 2023, but they started to rise from October. TrendForce believes that the three major global DRAM manufacturers have begun intensive production cuts, and as market demand begins to recover, the pricing power of memory manufacturers is gradually increasing.

In terms of DRAM supply in the fourth quarter, memory manufacturers have a clear upward pricing attitude, as TrendForce projects a noticeable increase of approximately 13-18% in contract prices during this period. However, the recovery in demand is not as strong as in previous peak seasons.

Overall, while there is demand for stocking up, in the current scenario, the server sector remains passive in terms of procurement due to high inventory levels. The shipment growth in the DRAM industry for the fourth quarter is expected to be limited.

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(Photo credit: Samsung)

Germany is currently caught in a budget dispute that led to the rejection of a planned multi-billion-euro official subsidy for semiconductor companies. Sources suggest that if the German government reduces the initially committed subsidy, TSMC might need to reopen discussions on its investment in a wafer fabs in Dresden, Germany. This would include revisiting agreements with German joint venture partners, with the worst-case scenario being the abandonment of the investment initiative.

According to Financial Times, an individual familiar with discussions between TSMC and the German government said, “Worst case is that if it turns out nine months from now that there will be no subsidies, we will have to cancel the project.”

Initially, the German government had pledged substantial support for foreign chipmakers investing in the country. Recently, the German cartel office officially approved Bosch, NXP, and Infineon’s involvement in TSMC’s German company, ESMC. Each of these companies will secure a 10% stake, while TSMC will maintain substantive control with over 50% ownership. The investment of EUR 10 billion to establish a wafer fab in Dresden has received a government commitment of EUR 5 billion in subsidies.

On the other hand, Intel, the semiconductor giant, had also planned a significant investment of EUR 30 billion for constructing two new fabs in Magdeburg, Eastern Germany, with a subsidy of EUR 9.9 billion. It is also the largest foreign investment since World War II.

However, the German Federal Constitutional Court’s recent ruling declared the shift of the initially allocated EUR 60 billion credit limit, intended for the new COVID-19 pandemic, to the “Climate Transformation Fund” as unconstitutional. The subsidies for chipmakers, including Intel and TSMC, from the German government were supposed to originate from this fund, raising industry-wide concerns due to the court’s decision.

German political and business figures, along with industry experts, express apprehension that semiconductors might become collateral damage in the budget dispute, potentially tarnishing Germany’s standing.

The current ESMC plan is still under observation for potential changes.  According to TrendForce’s previous research that ESMC’s initial total planned production capacity is approximately 40Kwspm. The fab is set to focus on 28/22nm and 16/12nm processes, with groundbreaking expected in the latter half of 2024 and full-scale production in 2027. Forecast from TrendForce suggest that TSMC’s overseas capacity share will rise from 9% in 2023 to 15% by 2027.

(Image: TSMC)

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On November 22, 2023, NVIDIA released its financial report for the third quarter of 2023 (FY3Q24: August 2023 to October 2023), with a revenue of USD 18.1 billion. This represents a quarterly increase of 34% and a yearly increase of 206%.

NVIDIA also provided a revenue guidance for the fourth quarter of 2023 (FY4Q24: November 2023 to January 2024), with a median estimate of USD 20 billion. This reflects a quarterly increase of 10.5% and a yearly increase of 231%.

TrendForce’s Insight:

1. Downgraded Chips Expected by Year-End 

NVIDIA continues its robust performance in the third quarter of 2023 (FY3Q24). The Datacenter division reported a revenue of USD 14.5 billion, marking a 41% quarterly increase and a staggering 279% annual increase. This segment now constitutes 80% of the overall revenue, with a 4% increase from the previous quarter.

The growth is primarily driven by the HGX Hopper GPU, along with the commencement of shipments and revenue recognition for L40S and GH200. Approximately 50% of Datacenter revenue comes from CSP customers, while the remaining 50% is contributed by Consumer Internet and enterprise clients.

In terms of revenue outlook, the China region accounts for approximately 20-25% of NVIDIA’s Datacenter revenue. The management acknowledges the significant impact of the U.S. restrictions on China’s revenue for the fourth quarter of 2023 but expresses confidence that revenue from other regions can offset this impact.

This confidence stems from the current high demand and low supply situation for AI chips. Notably, NVIDIA’s anticipated release of lower-capacity chips, including HGX H20, L20 PCIe, and L2PCIe, originally slated for November 16, 2023, is now expected to be delayed until the end of 2023, presumably due to ongoing negotiations with the U.S. Department of Commerce.

2. NVIDIA Unveils HGX H200, High-Capacity Version of H100; Next-Gen B100 Anticipates Doubling Performance

In a significant product announcement, NVIDIA introduced HGX H200 on November 14, 2023. The new offering is a high-capacity version of H100 and is fully compatible with HGX H100 systems. This compatibility ensures that manufacturers using H100 don’t need to modify server systems or software specifications when transitioning to H200.

HGX H200 is slated for release in the second quarter of 2024, with initial customers including AWS, Microsoft Azure, Google Cloud, and Oracle Cloud. Additionally, CoreWeave, Lambda, and Vultr are expected to adopt HGX H200 in their setups.

Comparing H200 SXM with H100 SXM, it’s evident that H200 SXM has a 76% increase in memory capacity and a 43% increase in bandwidth compared to H100 SXM. Additionally, it upgrades from HBM3 to HBM3e, while the remaining specifications remain the same. This indicates that H200 SXM is essentially a high-capacity version of H100 SXM.

Given the sensitivity of performance to memory capacity and bandwidth, inference on the Llama2 with 7 billion parameters shows that the performance of H200 SXM can reach 1.9 times that of H100 SXM.

Moreover, NVIDIA plans to launch the B100, truly representing the next generation of products with the new Blackwell architecture in 2024. Utilizing Chiplet technology, it is speculated that the architecture will transition from a single die + 6 HBM3 configuration in H100 to a dual-die + 8 HBM3e configuration in B100, potentially doubling the performance compared to H100.

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• [News] H200 Unveiled: NVIDIA Integrates HBM3e for Enhanced AI Performance

(Photo credit: NVIDIA)

The highly anticipated 18th International Microsystems, Packaging, Assembly, and Circuits Technology Conference, also known as IMPACT 2023, took place with grandeur from October 25th to 27th at Hall 1 of Taipei Nangang Exhibition Center. This prestigious event was co-organized by leading institutions in the fields of electronics, including IEEE Electronics Packaging Society (IEEE EPS) – Taipei, International Microelectronics Assembly and Packaging Society (iMAPS) – Taiwan, Industrial Technology Research Institute (ITRI), and the Taiwan Printed Circuit Association (TPCA). Under the overarching theme of “IMPACT on the Future of HPC, AI, and Metaverse,” the conference delved deep into the realm of cutting-edge IC packaging and circuit board technologies that are specifically tailored for next-generation applications in HPC, AI, and the Metaverse.

At the opening ceremony, Dr. Wei-Chung Lo, the Chair of IMPACT 2023, President of iMAPS – Taiwan, and Deputy Director of the Electronic and Optoelectronic System Research Laboratories at the ITRI, noted that the event had attracted over 700 participants, with nearly 30% from overseas. This made IMPACT 2023 the largest industry event for advanced semiconductor packaging technologies in Asia. Dr. Lo expressed gratitude for the support from the IEEE EPS, iMAPS, International Electronics Manufacturing Initiative (iNEMI), and Japanese associates including the International Conference on Electronic Packaging (ICEP) and Japan Institute of Electronics Packaging (JIEP). He also thanked the tremendous support from individuals and organizations across the industry and academia.

Innovations in Critical 3D Packaging Technologies and System-Level Performance Upgrade Will Trigger a Surge of New AI Applications

Following the opening ceremony, plenary speeches were delivered by Dr. Jun He, Vice President of Quality and Reliability and Operations and Advanced Packaging Technology and Service at TSMC, and Dr. Raja Swaminathan, Corporate Vice President at AMD. During his speech, Dr. He emphasized the explosive growth in the 3D packaging technology market, with a projected global market value exceeding USD 100 billion by 2025. Dr. He also highlighted TSMC’s proactive approach in aggressively promoting its “3DFabric” platform, which combines advanced packaging technologies such as SoIC (3D), CoWoS (2.5D), and InFO (2.5D). As a testament to the power of 3D packaging technology, he pointed out that NVIDIA’s latest generation GPU (i.e., the H100) has achieved a remarkable six-fold performance improvement compared to its predecessor (i.e., the A100).

The strong demand for HPC is fueling the extensive commercial adoption of 3D packaging technology. In light of this trend, TSMC plans to expand its cleanroom space for the 3D packaging process, with expectations of more than doubling it by 2025. Furthermore, TSMC is expediting collaborations with ecosystem partners to advance critical 3D packaging innovations. One example is hybrid bonding, which enhances interconnect density. Another example is key innovations in 3D packaging that optimize signal integrity for HBM.

▲Dr. Jun He, Vice President at TSMC, highlights the game-changing impact of 3D packaging technology on NVIDIA’s latest GPU, showcasing a remarkable six-fold performance improvement over its predecessor. The surge in demand for HPC is propelling the extensive adoption of 3D packaging technology across commercial applications. Anticipating this trend, TSMC is set to significantly expand its cleanroom space for 3D packaging, with plans to more than double it by 2025. (Source: IMPACT)

Dr. Swaminathan, Corporate Vice President of AMD, said that the demand for supercomputers and AI performance had previously been growing exponentially, doubling every 1.2 years. However, the growth rate has become even higher recently, doubling within a year. The industry’s primary focus lies in upgrading system-level performance through innovations in high-speed interfaces, advanced packaging, and heterogeneous integration. AMD, in particular, is directing its attention toward improving inter-chip communication and energy efficiency. Leveraging its evolving 3D stacking technology and hybrid bonding packaging, AMD aims to substantially reduce power consumption in inter-chip communication. AMD anticipates that it will achieve a 30-fold increase in HPC and AI training efficiency per watt over the next five years.

In summary, TSMC and AMD, as respective leaders in foundry services and IC design, are focusing on the synergistic relationship between advanced packaging technologies and next-generation AI architectures. They recognize that these two sets of technologies work together to drive substantial improvements in the computing capabilities of semiconductor chips.

▲AMD’s Corporate Vice President, Dr. Raja Swaminathan, stated that the 3D stacking and hybrid bonding technologies being developed by his company can significantly reduce the power consumption of inter-chip communication. AMD also forecasts a 30-fold increase in HPC and AI training efficiency per watt in the next five years. (Source: IMPACT)

Collaborative Design to Spark Major Transformations in AI, and High-Density Heterogeneous Integration Platform to Become Crucial Bridge to Future of Semiconductor Technology

This year’s conference marked the third edition of the IEEE EPS Panel Discussion / Forum, presided over by Dr. C. P. Hung, Vice President of the ASE Group. As a key organizer of the IMPACT conference, the IEEE EPS once again brought together the latest R&D findings and influential speakers to facilitate the exchange of information regarding the most recent trends and technological advancements within the semiconductor and electronics industries.

The inception of the IEEE EPS Panel Discussion has seen a progression of significant themes. The first edition centered on the realm of 5G, followed by the second edition that explored edge computing. Notably, this year’s panel was jointly organized with the IEEE Council on Electronic Design Automation (CEDA). The primary focus of this year’s panel discussion – also known as the IEEE EPS and CEDA Joint Panel – was on ECAD tools capable of optimizing the collaborative design process for chips, packages, and systems.

The idea to join forces with the IEEE CEDA originated from Dr. Bill Chen, Fellow and Senior Technical Advisor at the ASE Group. Delivering his remarks remotely from a different location, Dr. Chen emphasized that although AI and machine learning are still in their nascent stages, significant transformations are anticipated over the next few decades. Dr. Chen stressed that collaborative design will drive the development of AI-related products and applications. This trajectory of development will also necessitate the establishment of an open-source chip ecosystem and standardized interfaces to continuously improve efficiency.

▲Dr. C. P. Hung, Vice President of ASE Group and moderator of the IEEE EPS Panel Discussion, stated that this year’s theme, which was jointly developed with the IEEE CEDA, focuses on ECAD tools that optimize collaborative design across chips, packages, and systems. (Source: IMPACT)

In addition, the IEEE EPS and CEDA Joint Panel specially invited renowned scholars and experts from domestic and international backgrounds. Prominent speakers include Dr. Madhavan Swaminathan, Head of the Department of Electrical Engineering at Pennsylvania State University; Dr. Chih-ming Hung, MediaTek’s Assistant Vice President of Technology; Dr. Arvind Sundarranjan, Managing Director at the Applied Packaging Development Center (APDC); Dr. Kyu Lim Sung, Professor at the Georgia Institute of Technology; Dr. Debendra Das Sharma, Intel’s Senior Fellow; and Nan Wang, Vice President of Component Quality and Technology at Cisco.

Dr. Madhavan Swaminathan stressed that high-density heterogeneous integration platforms will be a future trend. Moreover, such platforms have to incorporate a wide range of technologies from antennas to AI to support applications related to network communication and edge computing. This means that R&D and collaborative design also have to take place simultaneously across various fields, with distributed computing and telecommunication solutions playing crucial roles. On the topic of AI-assisted design, Dr. Hung from MediaTek discussed the importance of synergy among material technology, mechanical engineering, EDA tools, etc. However, Dr. Hung also noted that not all advances in these fields have immediate practical uses in the development of AI applications. In the case of 3D AI machine learning, the maturity of the tools for training needs to be considered.

Turning to the topic of hybrid bonding, Dr. Madhavan Swaminathan pointed out that it is a key technology in advancing AI and HPC, as it brings about computing solutions that can handle massive amounts of data with reduced latency and greater power efficiency. On the other hand, hybrid bonding is a highly complex manufacturing process that involves at least hundreds of steps. Optimizing individual steps one at a time is not enough; synergistic progress has to take place across numerous sections of the process in order to raise the yield rate.

Dr. Sung believes that initiating the next wave of the “AI revolution” will require collaborations among various types of chips, and EDA tools provide the necessary support for the development of 2.5D and 3D packages. Besides being the indispensable assistant for chip designers, EDA tools can also contribute to decision-making regarding materials and bonding methods.

As for how the UCIe standard can contribute to the expansion of the ecosystem for small-sized chips, Dr. Debendra Das Sharma said that UCIe allows for the mixing and matching of multiple chips at the package level to overcome manufacturing limitations and increase yield rates. Currently supporting 2D and 2.5D packages, UCIe will also be introduced to 3D packages in the future. When building SoCs, this standard enables innovations at the package level, integrating not only CPU, GPU, and memory but also supporting interfaces such as USB, PCIe, and CXL. The adoption of UCIe is expected to result in dynamic and configurable systems.

Likewise, when discussing the topic of heterogeneous integration, Cisco’s Vice President Wang, mentioned Open Platform Communications (OPC), a set of standards and specifications for industrial telecommunication. Wang said that co-packaged optics, which falls under OPC, can effectively address the challenges related to power consumption and costs associated with the increasing demand from machine learning networks for high-speed connectivity and high-volume computing capability. With OPC technologies, optical components can be closely integrated with Ethernet switch ICs and packaged on the same substrate, thereby reducing system power consumption by as much as 30%. However, the adoption of OPC will bring new challenges related to the integrity of signals and power supply. Hence, collaborative design and system-level optimization are necessary to achieve large-scale application.

▲The IEEE EPS and CEDA Joint Panel featured a strong lineup of speakers. From left to right: Yao-wen Chang, Dean of the College of Electrical Engineering and Computer Science at National Taiwan University; Dr. Arvind Sundarranjan, Managing Director at the APDC; Dr. Chih-ming Hung, MediaTek’s Assistant Vice President of Technology; Dr. Madhavan Swaminathan, Head of the Department of Electrical Engineering at Pennsylvania State University; Dr. C. P. Hung, Vice President of ASE Group; Nan Wang, Vice President of Cisco; Dr. Kyu Lim Sung, Professor at the Georgia Institute of Technology; and Dr. Debendra Das Sharma, Senior Fellow at Intel. (Source: IMPACT)

Seeking the Best Collaborative Design Tools to Rapidly Address the Needs in the Market for Heterogeneous Integration Solutions

In the second half of the joint panel, Dr. Yao-wen Chang, Dean of the College of Electrical Engineering and Computer Science at National Taiwan University, took over as the moderator. He raised three questions for the experts to discuss and share their insights. The first question he posed was, “How can AI and advanced packaging technologies address the most challenging issues in the development of applications related to AI and edge computing?” Dr. Swaminathan from Penn State was the first to respond, explaining that AI requires large-scale computing and thus requires cooperation among chips made with different process nodes. This also means that advanced packaging technologies can facilitate the integration of various types of chips, including RF chips, GPUs, CPUs, and even optical components.

Dr. Hung from MediaTek cited successful cases of AI being applied to power supply analysis and chip layout optimization. However, the bottleneck in advancing 3D integration lies in the lack of data, so AI cannot fully replace humans in designing chips at the present moment. Dr. Sung also pointed to insufficient data related to circuit designs. This impose limitations in supervised learning. Currently, the academic community is ramping up research efforts in unsupervised learning and reinforcement learning. Cisco’s Vice President Wang said heterogeneous integration could address certain challenges in the development of network systems, but he also acknowledged that chip design and chip manufacturing could become more complex as a result.

▲IMPACT 2023 was a major gathering of elites in the semiconductor and electronics industries. The event attracted a huge number of professionals from various sectors to come to the venue and exchange market intelligence and ideas. (Source: IMPACT)

The second question was, “What are the key technological challenges that we must overcome when the next generation of AI interacts with human intelligence? And when can we expect to see solutions to these challenges?” In response to this question, Dr. Das Sharma said that heterogeneous integration can combine processors and memory in a single package, while 3D stacking can further narrow the distance of inter-chip communication, thereby leading to a faster data transfer rate, better performance, and less power consumption. Dr. Sundarrajan also pointed out that solving the challenges of heterogeneous integration will necessitate technological innovations in materials and other areas. Reducing the space between the chip and the substrate, lowering the defect rate, finding ways to strengthen the bond between different materials, and eliminating chip warping are some of the issues mentioned in the joint panel. These kinds of solutions are required to enable chips to achieve the most optimal performance.

The final question posed by Dr. Chang was, “Regarding EDA tools, what is the extent of their readiness for advanced packaging? And what are the major technological gaps that require immediate attention?” In answering this question, Dr. Sung said that the development of EDA tools is somewhat lagging behind when it comes to heterogeneous integration and the construction of 2.5D and 3D packages. Overall, chip designers need more functionality and automation from their EDA tools. While tools for 2D packages are quite mature, there is still considerable room for improvement in designing chips featuring 3D integration. Dr. Madhavan Swaminathan added that current providers of EDA tools tend to be too passive. They are reluctant to invest in new technologies without specific orders from customers. Swaminathan believes EDA companies need to partner with other technology developers to push forward heterogeneous integration.

Dr. Hung stated that even for 2D packages, chip design companies need to have their own in-house tools to address the shortcomings of commercial EDA tools from external providers. Dr. Hung believes EDA companies should respond more promptly to the needs of IC design houses. Turning to Dr. Das Sharma, he stated that when EDA companies see market potential, they will invest in new technologies. The key is to make them recognize that the aforementioned technologies represent the next major direction in the evolution of chip designs. Lastly, Cisco’s Wang called attention to the different integration and analytical capabilities that EDA tools and systems have to have in order to prepare for the potential issues that may arise in the future development of heterogeneous integration. Early preparations are essential.

▲The IEEE EPS and CEDA Joint Panel primarily delved into discussions on the following topics: (1) the use of AI and advance packaging technologies for resolving issues in the development of edge computing and AI-driven applications; (2) the major technological challenges in the development of next-generation AI; and (3) the use of EDA tools to further improve the designs of advanced packages. (Source: IMPACT)

As a collaborative effort between its organizers and a consortium of partnering entities, IMPACT 2023 unfolded as a massive three-day convention, featuring 33 sessions comprising seminars, panel discussions, lectures, and more. The event not only included keynote presentations by top executives from companies like TSMC and AMD but also assembled hundreds of heavyweight experts from academia and accomplished professionals from various industries worldwide. Additionally, the IEEE EPS and CEDAS Joint Panel was held for the first time, offering attendees an in-depth look into the realm of AI-based collaborative design. Embracing a holistic approach, IMPACT 2023 transcended mere technological discourse to explore the contours of market trends, igniting the sparks of innovation that promise to shape our future.

It is worth noting that TPCA Show 2023 was held concurrently, featuring 1,386 booths set up by companies around the world. More than 480 international brands were showcasing their products and services at this event. In terms of thematic focus, the exhibitions at TPCA Show 2023 were primarily about semiconductors (i.e., chip assembly and packaging), net-zero emissions, smart manufacturing, and forward-looking solutions. The organizers of TPCA Show 2023 were eager to provide a wide range of services to foreign visitors as they sought to make the event the premier international platform for presenting the latest innovations and trading cutting-edge solutions. Like IMPACT, TPCA Show aims to promote the development of various industries. These events also continue to demonstrate Taiwan’s capabilities in the areas of PCBs, semiconductors, electronics, etc.

(The featured image of this article shows Dr. Wei-chung Lo delivering the opening remarks on the first day of IMPACT 2023. Dr. Lo is the Chair of IMPACT 2023, President of iMAPS – Taiwan, and Deputy Director of the Electronic and Optoelectronic System Research Laboratories at ITRI. Source: IMPACT.)

On November 27, Kingston, the global leader in memory modules, and Longsys, acclaimed as key memory module maker in China, jointly announced the establishment of a new joint venture company in China. This strategic move aligns with the resurgence in the memory market, with Kingston taking the lead to step into the Chinese market, reported by UDN News.

As per the collaborative plans between Kingston and Longsys, the joint venture will be established in China, with Kingston holding a 51% stake and Longsys holding 49%. The focus is on expanding the Chinese market together. According to Longsys’ press release, the newly formed joint venture will operate independently, specializing in supplying embedded memory products to the Chinese market. Longsys will oversee product development and technical support, while Kingston will manage procurement and brand-related needs. The capital amount of the new company has not been disclosed by either Kingston or Longsys.

Founded in 1987 and headquartered in California, USA, Kingston is a globally renowned memory module product manufacturer. In 2022, it secured the top position in global memory module and solid-state drive module suppliers. Besides, it leads in the embedded storage market share and holds a dominant position as a key supplier to China’s Tier 1 OEM.

On the other hand, Longsys, established in 1999 and headquartered in Shenzhen, China, has emerged as a key player in the industry. In recent years, it acquired competitors such as Lexar in the United States and Smart Modular in Brazil. Longsys primarily focuses on NAND-related applications and is currently listed on the ChiNext board of the Shenzhen Stock Exchange.

In previous press release, TrendForce once mentioned that facing a volatile market in recent years, Chinese homegrown SSD channels are also actively advancing supply chain configurations. Aiming to step beyond China and into international waters, Chinese companies like Longsys is leading the charge by acquiring shares in Licheng Suzhou and Smart Modular to strengthen downstream module production capacity.

Regarding this joint venture, industry source anticipate that the partnership between Kingston and Longsys, with a focus on embedded storage products and NAND-related applications, will drive substantial demand for NAND chip control ICs.

(Image: Longsys)

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