In recent market speculations, TSMC is rumored to have reduced its 8-inch wafer manufacturing quotes by as much as 30%, with subsequent reports suggesting that South Korean wafer foundries are following suit in lowering 8-inch wafer production prices.

According to TrendForce’s channel check, TSMC’s current strategy for 8-inch processes involves bundling spot deal negotiations with one-time pricing or offering discounts and rebates on initial NRE fees, without implementing an across-the-board price cut.

However, observations from the order books indicate a genuine decline in demand for 8-inch products. Presently, customers have started revising their orders through the first quarter of 2024. The possibility of TSMC reducing prices for 8-inch wafers cannot be ruled out.

Similarly, the industry has also seen reports of South Korean wafer foundries Samsung and Dongbu HiTek considering price reductions for their 8-inch wafer plants. TrendForce indicates that the price adjustments in South Korea’s 8-inch wafer foundries follow a similar pattern of spot deal reductions, primarily centered around one-time negotiations. Customers with long-term agreement already have lower prices, without any instances of price reduction.

Both 12-inch and 8-inch wafer fabrication utilization rates have shown less-than-expected recovery, leading TrendForce to estimate a year-on-year decrease of around 13% in the overall semiconductor foundry revenue for 2023.

(Photo credit: TSMC)

According to a report by Taiwan’s Commercial Times, global smartphone brands are set to introduce a series of flagship-level new products. Following the introduction of Apple’s A17 chip using TSMC’s 3-nanometer process, Qualcomm’s next-generation processor Snapdragon 8 Gen 3 and MediaTek’s Dimensity 9300 are expected to be unveiled in October. These chips will be manufactured using TSMC’s N4P process, with plans to further transition to the N3E process next year.

Industry source have indicated that TSMC’s 3-nanometer yield is gradually improving, coupled with the return of N4P orders, providing a counterbalance against the impact of sluggish end market demand.

Commercial Times’ report highlights that TSMC previously expressed strong demand for its N3 process, projecting substantial growth in the second half of the year. The N3 process will support high-performance computing (HPC) and smartphone platforms, with an anticipated contribution of 4-6% to the company’s revenue in 2023. Additionally, N3E has already been verified and received its first batch of customer product design approvals, with mass production expected to commence in the fourth quarter. TSMC aims to achieve a monthly production capacity of 100,000 wafers in its 3-nanometer process by the end of the year to cater to Apple’s demands.

According to Bloomberg’s recent exposure of Apple’s projected M3 processor product roadmap set for release this fall, the basic M3 processor consists of 4 high-performance and 4 energy-efficient cores, paired with 10 GPU cores. M3 Pro comes in two versions: a basic version equipped with 12 cores (6 high-performance and 6 energy-efficient) and 18 GPU cores, and a higher-tier version with 14 CPU cores and 20 GPU cores.

M3 Max also offers two versions, featuring a fully-equipped 16-core CPU. The main difference between the basic and higher-tier versions lies in the GPU cores—32 for the former and a whopping 40 for the latter. The most powerful variant, M3 Ultra, essentially doubles the configuration of M3 Max, boasting 32 CPU cores paired with either 64 or 80 GPU cores. Industry experts widely regard TSMC as the primary beneficiary of these developments.

(Photo credit: TSMC)

Intel Corporation today announced that it has mutually agreed with Tower Semiconductor to terminate its previously disclosed agreement  to acquire Tower due to the inability to obtain in a timely manner the regulatory approvals required under the merger agreement, dated Feb. 15, 2022. In accordance with the terms of the merger agreement and in connection with its termination, Intel will pay a termination fee of $353 million to Tower.

In response to this development, TrendForce provides the following analysis:

As previously mentioned by TrendForce, Intel’s active entry into the semiconductor foundry market has presented challenges. These include:

Diversification of Manufacturing Expertise: Intel, historically focused on manufacturing CPUs, GPUs, FPGAs, and peripheral I/O chips, lacks the specialized fabrication processes possessed by other foundries. The success of acquiring Tower to expand its product line and market presence remains crucial.

Operational Segmentation: Apart from financial divisions, the division of physical facilities and actual production capacity must be strategically managed. Successfully emulating models like AMD/GlobalFoundries or Samsung LSI/Samsung Foundry, where there is a clear distinction between foundry and client, is essential. Simultaneously, Intel faces challenges in preventing orders from its significant client, the Intel Design Department, from flowing outward.

The official termination of the Tower acquisition plan introduces greater uncertainties and challenges for Intel in the competitive foundry market. In an industry marked by heightened competition, having dominance in specialized process technologies and diversified production lines is pivotal for sustaining profitability amid industry downturns. Without the assistance of Tower’s established specialized processes, Intel’s strategic approach and technology development in the foundry business will be worth monitoring.

(Photo credit: Intel)

DRAM Spot Market:

The spot market has shown no demand turnaround this week, so prices there are stagnant. Unlike the situation in the contract market, suppliers are not collectively attempting to moderate the price decline in the spot market due to the lack of a notable rebound in the sales of consumer electronics. Also, high inventories held by module houses are keeping spot prices on a downward trajectory. On the whole, spot prices of DDR4 and DDR5 products continue to show daily drops. The average spot price of the mainstream chips (i.e., DDR4 1Gx8 2666MT/s) fell by 0.07% from US$1.461 last week to US$1.460 this week.

NAND Flash Spot Market:

The spot market is seen with a recovery of purchase willingness this week due to the power outage at SK hynix, though TrendForce’s survey confirms that the particular incident has not yielded any impact towards market supply. Low-priced transactions no longer exist among spot prices of NAND Flash after suppliers’ significant drop of production in 2H23, and the declination that lasted for several consecutive weeks is now halted. 512Gb TLC wafer spots have risen by 0.28% this week, arriving at US$1.440.

According to a report by Taiwan’s Commercial Times, JPMorgan’s latest analysis reveals that AI demand will remain robust in the second half of the year. Encouragingly, TSMC’s CoWoS capacity expansion progress is set to exceed expectations, with production capacity projected to reach 28,000 to 30,000 wafers per month by the end of next year.

The trajectory of CoWoS capacity expansion is anticipated to accelerate notably in the latter half of 2024. This trend isn’t limited to TSMC alone; other players outside the TSMC are also actively expanding their CoWoS-like production capabilities to meet the soaring demands of AI applications.

Gokul Hariharan, Head of Research for JPMorgan Taiwan, highlighted that industry surveys indicate strong and unabated AI demand in the latter half of the year. Shortages amounting to 20% to 30% are observed with CoWoS capacity being a key bottleneck and high-bandwidth memory (HBM) also facing supply shortages.

JPMorgan’s estimates indicate that Nvidia will account for 60% of the overall CoWoS demand in 2023. TSMC is expected to produce around 1.8 to 1.9 million sets of H100 chips, followed by significant demand from Broadcom, AWS’ Inferentia chips, and Xilinx. Looking ahead to 2024, TSMC’s continuous capacity expansion is projected to supply Nvidia with approximately 4.1 to 4.2 million sets of H100 chips.

Apart from TSMC’s proactive expansion of CoWoS capacity, Hariharan predicts that other assembly and test facilities are also accelerating their expansion of CoWoS-like capacities.

For instance, UMC is preparing to have a monthly capacity of 5,000 to 6,000 wafers for the interposer layer by the latter half of 2024. Amkor is expected to provide a certain capacity for chip-on-wafer stacking technology, and ASE Group will offer chip-on-substrate bonding capacity. However, these additional capacities might face challenges in ramping up production for the latest products like H100, potentially focusing more on older-generation products like A100 and A800.

(Photo credit: TSMC)