Major economies are investing heavily in semiconductor industries, with China leading at $143 billion, the U.S. at $52.7 billion, and the EU at $47 billion, according to “EE Times”. India plans to give $922 million amid U.S.-China tensions.

Despite China’s much larger subsidies compared to India’s, the Chinese semiconductor industry faces various challenges. But under mainly from the United States, to slow down its progress, some Chinese companies are struggling to survive, while others are shutting down. For instance, after OPPO’s unexpected announcement in May to close their IC design company ZEKU, active for less than 4 years, Holding Group, Geely, also declared on August 8th that it would halt its self-developed chip business through the Xingji Meizu group, only 5 months after its launch.

According to a recent report from ‘EE Times,’ governments from around the world are actively pursuing semiconductor self-sufficiency to meet their high-tech and communication needs. China, in particular, has taken the lead by planning a substantial $143 billion subsidy program to boost its industry and reduce dependence on the United States.

In the U.S., the ‘Chips ACT’ passed last year allocated $52.7 billion in subsidies. As per McKinsey, the cumulative commercial investments related to this endeavor have already exceeded $200 billion.

The European Union is also making its mark, aiming to increase its global semiconductor market share from 10% to 20% by 2030. The ‘European Chips Act’ is expected to see $47 billion in government investment. TSMC has confirmed plans to establish a factory in Germany and is expected to receive relevant subsidies.

Singapore is projecting a $19 billion subsidy for its semiconductor industry, while Japan’s exact subsidy scale remains unknown, with reports suggesting a minimum of $6.5 billion. South Korea is focusing on tax reductions for semiconductor-related companies, offering 15% tax credits for corporate groups and up to 25% for small and medium-sized enterprises.

Recently, the UK and India have joined the battle. The UK has set aside a $1.5 billion subsidy, and India’s ‘Semicon India’ initiative offers at least $922 million to bolster its influence in the global electronics supply chain. While Malaysia hasn’t disclosed the amount of support for its chip industry, the country is providing approved priority industries, especially high-tech firms, with a full 10-year tax exemption. The government also offers investment subsidies and various incentives within specific investment zones.

Amidst U.S. restrictions, China initially aimed to boost its chip industry and create its own ‘China chips.’ However, setbacks have occurred. OPPO’s IC design company, ZEKU, formed in 2019, spent a staggering $44 billion over three years only to shut down on May 12th, leaving 3,000 employees jobless. Geely Holding Group’s subsidiary, Xingji Meizu, also announced on August 8th their decision to halt self-developed chip operations due to global economic uncertainties. Their focus will now turn to product innovation and software user experiences.

(Source: https://ec.ltn.com.tw/article/breakingnews/4392195)

As semiconductor process technology nears known physical limits, the spotlight among major industry players is shifting towards the development of advanced packaging. Concurrently, the rise of applications like artificial intelligence and AIGC has propelled the concept of advanced packaging into a new technological wave. In the midst of the semiconductor industry’s global competition, securing more orders has become a core objective for major players.

A Competitive Landscape in Advanced Packaging

The competition in advanced packaging technology is intensifying, with companies pouring substantial investments into the field, resulting in a landscape of vigorous competition. Various packaging technologies have emerged, with notable offerings from industry giants such as TSMC, Intel, and Samsung.

TSMC introduced 3DFabric, an integration of its TSMC-SoIC front-end technology with CoWoS and InFO back-end technologies, providing maximum flexibility for diverse innovative product designs.

Intel, on the other hand, features its 2.5D EMIB and 3D Foveros packaging technologies. EMIB is applied in the connection of logic chips and high-bandwidth memory, as seen in the Intel Xeon Max series and Intel Data Center GPU Max series.

Foveros allows top dies to overcome size limitations and accommodate more top and base dies, connected through copper pillars to reduce potential interference from through-silicon vias (TSVs).

Samsung also exhibits strong competitiveness in advanced packaging, with its 2.5D I-Cube4 and H-Cube, along with 3D X-Cube packaging technologies, achieving breakthroughs in multi-chip interconnects and integration.

Samsung’s I-Cube4, for example, integrates four HBM stack dies and one core compute IC on the silicon interposer layer, while H-Cube enhances packaging area through the stacking of HDI PCBs to accommodate designs with six or more HBM stack dies.

Advantages of the Three Giants

In recent years, the three semiconductor giants have directed substantial capital expenditure towards advanced packaging. Their diverse technological developments and marketing strategies are poised to ignite a global battle in the semiconductor advanced packaging industry.

TSMC holds the advantage with its dominant wafer process technology and an end-to-end comprehensive service approach. Coupled with Taiwan’s robust semiconductor ecosystem, TSMC leads the way in the advanced packaging domain.

Intel, while slightly trailing TSMC in advanced process technology, matches it in advanced packaging capabilities. Emphasizing flexible foundry services, Intel allows clients to mix and match its wafer manufacturing and packaging offerings. With manufacturing facilities scattered worldwide, Intel leverages geographic advantages, particularly in Western countries, to expand capacity and services, leading to anticipated gains in the future.

Samsung, like TSMC, offers end-to-end services, but its packaging technology lags behind TSMC’s. It secures a share in constrained supply situations. Notably, Samsung, in June 2022, was ahead of TSMC in unveiling the innovative GAA 3nm process, and is poised to combine it with 3D packaging technology, potentially marking a pivotal point in the next semiconductor generation.

With semiconductor technology’s continuous evolution and surging market demand, the competition among the three giants in advanced packaging will remain fierce. While wafer fabs currently prioritize processes, the next three to five years are expected to witness a gradual shift towards advanced packaging. Different packaging technologies and marketing strategies will ultimately determine companies’ positions and influence in the market.

(Photo credit: TSMC)

Read more:

• An In-Depth Explanation of Advanced Packaging Technology: CoWoS
• ASE, Amkor, UMC and Samsung Getting a Slice of the CoWoS Market from AI Chips, Challenging TSMC

According to a report by Taiwan Economic Daily, industry sources have revealed that due to sluggish terminal demand and market competition, TSMC and Vanguard have recently been progressively lowering their prices for 8-inch wafer foundry services, with reductions as high as 30%.

While 8-inch wafer foundry services do not constitute a major portion of TSMC’s revenue, the company has historically maintained a relatively steadfast pricing strategy, refraining from frequent price hikes or reductions. The current reduction of up to 30% has raised significant attention.

The report states that the semiconductor industry is experiencing a downturn in prosperity, resulting in decreased capacity utilization at wafer foundries. Within this context, demand for 8-inch wafers is weaker compared to 12-inch wafers, leading some manufacturers to see their 8-inch wafer utilization rates drop to around 60%.

Regarding the price reduction, analysts at Nomura Securities suggest that this move is primarily aimed at countering Texas Instruments (TI), a global leader in analog ICs, which has significantly lowered prices for products such as power management ICs, triggering a worldwide semiconductor price war that has impacted related industries. In response, IC design companies are hoping for price reductions from foundries such as TSMC and to lower costs and compete against TI.

IC design firms have indicated that they have not received any official notification of price reductions for 8-inch wafer foundry services. They emphasized that TSMC has never implemented such a substantial reduction of up to 30% since its establishment, raising doubts about the authenticity of the news. TSMC has declined to comment on pricing matters.

(Photo credit: TSMC)

TSMC previously announced in November 2021 that it plans to establish two wafer fabrication plants for the 7nm and 28nm processes in Kaohsiung, a southern city of Taiwan. Construction was set to begin in 2022, with official production expected to commence in 2024. However, following the announcement, there have been changes in the progress of the Kaohsiung plant development.

Firstly, there were reports of adjustments to the 7nm plant by the end of 2022, in response to weakened demand in the smartphone and PC markets. Subsequently, there were also reports of changes to the 28nm plant’s plans.

It wasn’t until TSMC’s Q1 2023 earnings conference that they officially announced the adjustment of the Kaohsiung 28nm plant’s construction plans, focusing on capacity enhancement for more advanced process technologies.

At the time, TSMC didn’t specify the exact advanced process that would be introduced, only emphasizing that the construction of the wafer fab would proceed as planned. This triggered market speculation that TSMC was likely to adopt the advanced 2nm process technology at the Kaohsiung plant, in response to the rapidly growing demand in the artificial intelligence market.

This week, TSMC confirmed that the Kaohsiung plant will adopt the 2nm process technology. TSMC stated that the construction of the wafer fab in Kaohsiung will proceed as usual, but the previous expansion plans will be adjusted to accommodate the production of the 2nm advanced process technology, in response to strong market demand for advanced processes.

As for the specific details and contents of the plant development, they have not been further disclosed at this stage. According to TSMC’s plans, mass production of the 2nm process is expected to begin in 2025, with production bases including the previously announced Hsinchu and Taichung facilities, as well as the newly announced Kaohsiung facility.

(Photo credit: TSMC)

SK Hynix, a semiconductor leader, announced a significant breakthrough in NAND flash technology on August 9 at the Flash Memory Summit in California. They introduced a pioneering 321-layer 1Tb TLC 4D NAND flash memory, marking a notable advancement in NAND capabilities.

As the first company in the industry to surpass 300 layers in NAND development, SK Hynix plans to refine the 321-layer NAND for mass production by mid-2025. This leap builds upon their expertise gained from 238-layer NAND production, showcasing their commitment to pushing technological boundaries.

The efficiency of the 321-layer NAND is 59% higher than its 238-layer predecessor, attributed to enhanced data storage unit stacking. This translates to increased storage capacity and improved chip output per wafer.

In response to the growing demand for high-performance memory solutions in the AI market, SK Hynix unveiled next-gen NAND products, including PCIe 5-equipped enterprise SSDs and UFS 4.0 solutions, catering to the increasing need for advanced storage.

SK Hynix’s dedication to innovation is further emphasized by its ongoing development of PCI 6.0 and UFS 5.0 products, solidifying its market leadership position. Meanwhile, VP of SK Hynix NAND Flash Development, affirmed their commitment to leading the NAND technology domain with the development of fifth-gen 321-layer 4D NAND, tailored to the AI era.

(Source: https://mp.weixin.qq.com/s/OJ3_hw2jQuXT5YGiX0K8-Q)