DRAM Spot Market
Compared with last week, there are signs that the decline in DRAM spot prices is easing, but there has not been a noticeable increase in overall transaction volume. The spot market still has an abundant supply of DDR4 products mainly due to the influx of rebelled chips from decommissioned server DRAM modules. As a result, DDR4 products are under greater pressure to sell compared with DDR5 products. Currently, consumer 1Gx8 DDR4 chips are priced around US$0.88-0.9, while those from CXMT are priced around US$1. DDR4 chips from other suppliers are mostly being sold to customers in the industrial equipment segment, resulting in higher spot prices of around US$1.4. DDR5 products have relatively stable spot prices as they belong to the new generation and their supply has not been affected by recalled products. The average spot price of DDR5 2Gx8 chips from suppliers is now above US$4. In sum, DRAM spot prices are not showing signs of a rebound in the near future, mainly due to sluggish demand and an excess supply of DDR4 products. The average spot price of mainstream chips (DDR4 1Gx8 2666MT/s) dropped by 0.41% from US$1.468 last week to US$1.462 this week.

NAND Spot Market
Peak season effects are yet to be seen from the demand end, where NAND Flash suppliers’ successive increase of quotations has not ramped up stocking dynamics as some module houses have long raised their inventory, and the retail market is experiencing a poor level of actual transactions without aggressive price negotiations. Prices are maintained at a consolidation this week. 512Gb TLC wafer spots have risen by 1.06% this week, arriving at US$1.436.

Leading semiconductor companies TSMC, Robert Bosch GmbH, Infineon, and NXP Semiconductors have jointly to invest in the European Semiconductor Manufacturing Company (ESMC) GmbH, situated in Dresden, Germany. This strategic move aims to bolster the region’s semiconductor manufacturing capabilities, particularly catering to the burgeoning automotive and industrial sectors. The establishment of ESMC marks a significant stride towards the realization of a 300mm fabrication facility, pending the final decision on public funding, as part of the European Chips Act framework.

The planned fab is expected to have a monthly production capacity of 40,000 300mm (12-inch) wafers on TSMC’s 28/22 nanometer planar CMOS and 16/12 nanometer FinFET process technology, further strengthening Europe’s semiconductor manufacturing ecosystem with advanced FinFET transistor technology and creating about 2,000 direct high-tech professional jobs. ESMC aims to begin construction of the fab in the second half of 2024 with production targeted to begin by the end of 2027.

The prospective joint venture will see TSMC holding a substantial 70% ownership stake, while Bosch, Infineon, and NXP will each possess a 10% equity share, contingent upon regulatory approvals and meeting specific conditions. Total investments exceeding 10 billion euros are anticipated. Operational oversight of the fabrication facility will reside under TSMC’s purview.

However, industry analysts at TrendForce have highlighted potential challenges that lie ahead for TSMC’s groundbreaking endeavor. One such challenge pertains to the looming labor shortage issue in TSMC’s US fabrication facility, which is projected to reverberate globally. Moreover, navigating the intricacies of implementing subsidy policies in accordance with the European chip legislation and anticipated administrative procedures is expected to introduce a layer of complexity to the venture.

(Photo credit: TSMC)

Charlie Boyle, Vice President of NVIDIA’s DGX Systems, recently addressed the issue of limited GPU production at the company.

Boyle clarified that the current GPU shortage is not a result of NVIDIA misjudging demand or constraints in Taiwan Semiconductor Manufacturing Company’s (TSMC) wafer production. The primary bottleneck for GPUs lies in the packaging process.

It’s worth noting that the NVIDIA A100 and H100 GPUs are currently manufactured by TSMC using their advanced CoWoS (Chip-on-Wafer-on-Substrate) packaging technology. TSMC has indicated that it may take up to a year and a half, including the completion of additional wafer fabs and expansion of existing facilities, to normalize the backlog of packaging orders.

Furthermore, due to the significant strain on TSMC’s CoWoS capacity, there have been reports of overflow of NVIDIA GPU packaging orders to other manufacturers.

Sources familiar with the matter have revealed that NVIDIA is in discussions with potential alternative suppliers, including Samsung, as secondary suppliers for the 2.5D packaging of NVIDIA’s A100 and H100 GPUs. Other potential suppliers include Amkor and the Siliconware Precision Industries Co., Ltd. (SPIL), a subsidiary of ASE Technology Holding.

In December 2022, Samsung established its Advanced Packaging (AVP) division to seize opportunities in high-end packaging and testing. Sources suggest that if NVIDIA approves of Samsung’s 2.5D packaging process yield, a portion of AI GPU packaging orders may be placed with Samsung.

TrendForce’s research in June this year indicated that driven by strong demand for high-end AI chips and High-Bandwidth Memory (HBM), TSMC’s CoWoS monthly capacity could reach 12,000 units by the end of 2023. Particularly, demand from NVIDIA for A100 and H100 GPUs in AI servers has led to nearly a 50% increase in CoWoS capacity compared to the beginning of the year. Coupled with the growth in demand for high-end AI chips from companies like AMD and Google, the second half of the year is expected to witness tighter CoWoS capacity. This robust demand is projected to continue into 2024, with advanced packaging capacity potentially growing by 30-40% if the necessary equipment is in place.

(Photo credit: NVIDIA)

Leading semiconductor companies are making significant strides in global expansion with the announcement of two new fabrication facilities. TSMC is set to greenlight a factory in Germany, while GlobalFoundries plans to establish its first 12-inch wafer plant in Singapore.

TSMC’s Bold Move: Germany’s Green Light

TSMC from its presence in the USA, China (Shanghai and Nanjing), to Japan (Kumamoto City), TSMC’s global manufacturing footprint is expanding. Reuters reported on August 7 that TSMC’s board is inclined to approve the construction of a plant in Dresden, Germany. The German government pledges a substantial 5 billion euros (about $5.49 billion USD) to support the facility. However, the German Ministry of Economy refrains from commenting on the matter.

TSMC has been negotiating with the Saxony German state since 2021 to establish a collaborative FAB plant. In partnership with Bosch, Infineon, and Onsemi, TSMC aims to utilize the Dresden plant primarily for automotive chip production. Pending board approval, this venture could involve financing discussions with Berlin, ultimately requiring European Commission endorsement. TSMC, Intel, and Wolfspeed stand out among chip manufacturers seeking government assistance for European manufacturing ventures.

GlobalFoundries Poised to Build 12-Inch Wafer Plant in Singapore

According to udn.com, GlobalFoundries is set to make a substantial investment in the establishment of a 12-inch wafer fabrication plant in Singapore. The project’s funding could exceed NT$100 billion (approximately $3.2 billion USD). Reports suggest that this Singaporean facility will focus on producing 28-nanometer chips, with a potential completion date as early as 2026.

Industry experts note that GlobalFoundries’ move to set up a 12-inch facility in Singapore implies a significant shift in the competitive landscape. TSMC, UMC, PSMC, and GlobalFoundries – the four major semiconductor foundries – will all possess 12-inch production capabilities. Additionally, each of these companies has international expansion plans for such facilities. Notably, TSMC’s ventures span across the USA and Japan, UMC, and GlobalFoundries are both targeting Singapore, while PSMC’s strategy involves establishing a plant in Japan in collaboration with local partners.

Major Manufacturers Expand Against the Current Downturn

TSMC has been proactive in its expansion strategy, unveiling plans for ten new facilities in the past two years. These include 5 wafer plants and 2 advanced packaging facilities in Taiwan, alongside 3 overseas wafer plants. Despite the industry’s current challenges, TSMC’s expansion momentum remains strong, driven by a heightened focus on global manufacturing diversity.

TSMC is well aware of the potential risks tied to significant expansion efforts. In its latest annual report, the company acknowledges that expanding on a global scale demands substantial resources, highlighting possible challenges like rising costs, workforce shortages, disasters, land scarcity, cyber threats, government support, cultural differences, intellectual property protection, and tax variations.

Expanding during a semiconductor downturn has become a strategic approach for the foundry players. Typically, a fab construction takes 2 to 4 years, with equipment installation lasting 0.5 to 1 year and production ramp-up stretching 1 to 2 years. Looking ahead, semiconductor foundries are gearing up for a fresh wave of capacity release throughout 2024 and 2025.

Despite the industry’s ongoing slump, encouraging signs suggest that the downturn might be reaching its conclusion. Industry experts are cautiously optimistic, anticipating the arrival of the next upswing in the cycle.

(Source: https://mp.weixin.qq.com/s/4Xu_uc58kG85E_6R4Y3qhQ)

Over the past few decades, semiconductor manufacturing technology has evolved from the 10,000nm process in 1971 to the 3nm process in 2022, driven by the need to increase the number of transistors on chips for enhanced computational performance. However, as applications like artificial intelligence (AI) and AIGC rapidly advance, demand for higher core chip performance at the device level is growing.

While process technology improvements may encounter bottlenecks, the need for computing resources continues to rise. This underscores the importance of advanced packaging techniques to boost the number of transistors on chips.

In recent years, “advanced packaging” has gained significant attention. Think of “packaging” as a protective shell for electronic chips, safeguarding them from adverse environmental effects. Chip packaging involves fixation, enhanced heat dissipation, electrical connections, and signal interconnections with the outside world. The term “advanced packaging” primarily focuses on packaging techniques for chips with process nodes below 7nm.

Amid the AI boom, which has driven demand for AI servers and NVIDIA GPU graphics chips, CoWoS (Chip-on-Wafer-on-Substrate) packaging has faced a supply shortage.

But what exactly is CoWoS?

CoWoS is a 2.5D and 3D packaging technology, composed of “CoW” (Chip-on-Wafer) and “WoS” (Wafer-on-Substrate). CoWoS involves stacking chips and then packaging them onto a substrate, creating a 2.5D or 3D configuration. This approach reduces chip space, while also lowering power consumption and costs. The concept is illustrated in the diagram below, where logic chips and High-Bandwidth Memory (HBM) are interconnected on an interposer through tiny metal wires. “Through-Silicon Vias (TSV)” technology links the assembly to the substrate beneath, ultimately connecting to external circuits via solder balls.

The difference between 2.5D and 3D packaging lies in their stacking methods. 2.5D packaging involves horizontal chip stacking on an interposer or through silicon bridges, mainly for combining logic and high-bandwidth memory chips. 3D packaging vertically stacks chips, primarily targeting high-performance logic chips and System-on-Chip (SoC) designs.

When discussing advanced packaging, it’s worth noting that Taiwan Semiconductor Manufacturing Company (TSMC), rather than traditional packaging and testing facilities, is at the forefront. CoW, being a precise part of CoWoS, is predominantly produced by TSMC. This situation has paved the way for TSMC’s comprehensive service offerings, which maintain high yields in both fabrication and packaging processes. Such a setup ensures an unparalleled approach to serving high-end clients in the future.

Applications of CoWoS

The shift towards multiple small chips and memory stacking is becoming an inevitable trend for high-end chips. CoWoS packaging finds application in a wide range of fields, including High-Performance Computing (HPC), AI, data centers, 5G, Internet of Things (IoT), automotive electronics, and more. In various major trends, CoWoS packaging is set to play a vital role.

In the past, chip performance was primarily reliant on semiconductor process improvements. However, with devices approaching physical limits and chip miniaturization becoming increasingly challenging, maintaining small form factors and high chip performance has required improvements not only in advanced processes but also in chip architecture. This has led to a transition from single-layer chips to multi-layer stacking. As a result, advanced packaging has become a key driver in extending Moore’s Law and is leading the charge in the semiconductor industry.

(Photo credit: TSMC)