Mature process foundries are locked in a battle to uphold a 60% capacity utilization rate. Reports indicate that major players, including UMC, Vanguard International Semiconductor (VIS), and PSMC, are slashing prices significantly for the first quarter of the coming year to salvage their capacity utilization rates. This reduction, reaching double-digit percentages and up to 15% to 20% for project customers, stands out as the most extensive post-pandemic price cut, according to UDN News.

Post-Pandemic Price Challenges in Mature Process Foundries    

This pricing adjustment is pushing the prices of mature process foundries to a new low post-pandemic, affecting the profit margins and profitability trends of related companies. Industry sources disclose that only TSMC’s prices remain robust, with almost no exception for other foundries.

To rescue capacity utilization rates, companies are aggressively tweaking their quotes. A source from an IC design company privately reveals that foundries have notified them of slow-moving business in mature processes, resulting in a direct drop in capacity utilization rates. To ensure capacity utilization rates and market share, maintaining a certain level of production scale becomes imperative, prompting a substantial reduction in quotes.

Industry sources emphasize that despite recent indications of recovery in the PC and smartphone markets, clients remain cautious due to external factors such as inflation, especially given almost a year of inventory clearance. Companies, still on edge, fear slipping back into the challenges of inventory clearance and thus maintain a conservative approach to order placement.

Currently, the recovery in order placement strength is only about 30% to 40% of pre-pandemic levels, compelling wafer foundries to intensify their price cuts to prevent orders from being lost to competitors willing to lower prices, resulting in even lower capacity utilization.

It is evident that consumer IC demand for foundry services is low, and whom focusing on 8-inch mature process are the most affected. It is mainly due to excessive duplicate orders from integrated device manufacturers (IDMs) and IC design companies in the past, leading to inventory clearance for chips such as power management ICs, driver ICs, and microcontrollers (MCUs). Some products have even shifted to 12-inch wafers, keeping the capacity utilization rates of 8-inch foundries at a low level.

Navigate Semiconductor Shifts in TSMC, UMC, VIS, and PSMC

Industry sources note that TSMC is bolstered by advanced processes, enabling them to bundle them with mature processes for sale. Moreover, TSMC’s pricing strategy for mature processes has not surged as dramatically as that of other related companies, making it more acceptable to customers.

As for UMC, the company anticipates a drop in capacity utilization rates from 67% in the last quarter to 60% to 63% in this quarter, reaching a single-season low in recent years. Due to the continuous adjustment of capacity utilization rates, the gross profit margin will drop from 35.9% last quarter to 31% to 33%, reverting to levels seen at the beginning of the pandemic in 2021.

In response to pricing issues, UMC stated that, as mentioned in a recent earnings call, there will indeed be a significant decrease in the 8-inch, but there will be no adjustments for the 12-inch. Supply chain sources reveal that UMC has reportedly offered a 5% concession, aiming to consolidate order momentum with major clients this quarter. Considering the anticipated weak demand in the first quarter of next year and to attract more order placements, UMC plans to expand the price reduction to double-digit percentages.

According to the supply chain, VIS is expected to see a price reduction of up to 5% in the second half of the year. Large-volume clients may even secure a 10% discount, with a further decrease expected in the first quarter of next year, ranging from single to double-digit percentages. The company’s management previously mentioned at a conference call that, in response to intense price competition, short-term flexible adjustments are anticipated.

Similarly impacted by conservative customer order placements, PSMC reported losses in the third quarter, with capacity utilization rates hovering around 60%. It is reported that PSMC is also gearing up to implement price reduction measures to enhance capacity utilization rates.

(Image: VIS)

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Mainland China’s 3D NAND flash memory manufacturer, Yangtze Memory Technologies Co. (YMTC), filed a lawsuit against the U.S. memory chip leader, Micron Technology, on November 9th in the Northern District Court of California. The lawsuit accuses Micron of infringing upon eight of YMTC’s U.S. patents related to 3D NAND technology.

According to ICsmart, the patents involved in this case from YMTC include US10,950,623 (3D NAND memory device and method of forming the same), US11,501,822 (Non-volatile storage device and control method), US10,658,378 (Through-array contact [TAC] for three-dimensional memory devices), and US10,937,806 (Through-array contact [TAC] for three-dimensional memory devices), US10,861,872 (Three-dimensional memory device and method for forming the same), US11,468,957 (Architecture and method for NAND memory operation), US11,600,342 (Method for reading three-dimensional flash memory), and US10,868,031 (Multiple-stack three-dimensional memory device and fabrication method  thereof).

In the complaint, YMTC alleges that Micron’s 128-layer, 176-layer, and other series of 3D NAND technology have violated eight patents owned by YMTC. Micron is accused of using YMTC’s patented technology without authorization to compete with YMTC, protecting market share and impeding YMTC’s interests, thereby inhibiting innovation.

In recent years, with the stacking of 3D NAND technology reaching 128 layers and even higher, the chip area occupied by peripheral CMOS circuits may exceed 50%. To address this issue, YMTC introduced its proprietary innovative Xtacking technology in 2018.

Established in July 2016 and headquartered in Wuhan, Hubei, YMTC is an IDM (Integrated Device Manufacturer) specializing in the design and manufacturing of 3D NAND flash memory. It also provides comprehensive memory solutions.

Under the shadow of the ongoing US-China tech rivalry, Micron Technology adopted a low-key approach at this year’s Import Expo in Shanghai. During a meeting with Micron’s CEO, Sanjay Mehrotra, Chinese Minister of Commerce Wang Wentao on November 1st welcomed Micron’s continued presence and expansion in the Chinese market, emphasizing the importance of adhering to Chinese laws and regulations for sustainable development. Mr. Mehrotra expressed the company’s willingness to further invest in China.

However, on May 21st this year, China’s Cyberspace Administration announced serious cybersecurity issues with Micron’s products sold in China. These products didn’t pass the review, leading Chinese operators to halt the purchase of Micron’s products. This indicates a potential ban on Micron’s products in the Chinese market.

In October 2022, the US imposed exprt restrictions on advanced chip manufacturing equipment, including placing 36 Chinese companies such as YMTC on an entity list.

(Photo credit: iStock)

The demand for TSMC’s CoWoS advanced packaging is skyrocketing. Following NVIDIA’s expansion confirmation in October, there are reports in the industry that major clients like Apple, AMD, Broadcom, Marvell, and others are also placing additional orders with TSMC.

To meet the demands of these five major clients, TSMC is fast-tracking the expansion of CoWoS advanced packaging capacity. Next year, the monthly capacity will increase by about 20% more than the original doubling target, reaching 35,000 wafers, reported by UDN News.

TSMC has not commented on the capacity deployment for CoWoS advanced packaging. Industry sources believe that the substantial orders from TSMC’s major clients indicate a widespread growth in AI applications, driving the demand for chips such as GPU and AI accelerators.

In response to the continuous increase in AI demand, TSMC had previously announced the doubling of CoWoS advanced packaging capacity expansion for next year but did not disclose the monthly production capacity. Industry reports suggest that TSMC’s CoWoS advanced packaging capacity next year will not only double but will also increase by an additional 20% from the original target, resulting in a total monthly capacity of 35,000 wafers.

NVIDIA currently stands as the main large customer for TSMC’s CoWoS advanced packaging, securing almost 60% of TSMC’s related capacity, which is used in its AI chips such as H100 and A100. Additionally, AMD’s latest AI chip products are in the mass production stage, and the upcoming MI300 chip, expected to launch next year, will adopt both SoIC and CoWoS advanced packaging.

At the same time, Xilinx, a subsidiary of AMD, has been a significant customer for TSMC’s CoWoS advanced packaging. With the continuous growth in AI demand, not only Xilinx but also Broadcom has started increasing orders for TSMC’s CoWoS advanced packaging capacity.

(Image: TSMC)

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Akira Amari, a Japanese lawmaker and leader of the parliamentary association to promote semiconductor strategy, reveals that Japan is gearing up to allocate a subsidy of up to 900 billion yen for the second-phase expansion of TSMC’s Kumamoto fab. The plan involves transitioning from the 22/28 nm and 12/16 nm processes to the more advanced 7 nm process. Once completed, Japan is anticipated to emerge as the leading semiconductor supply hub globally.

Media reports suggest that the cabinet amendment is expected to allot a total of 1.9 trillion yen for semiconductor subsidies in Japan. Japanese companies are slated to receive 590 billion yen, while TSMC’s second-phase expansion project in Kumamoto is in line for the highest subsidy of 900 billion yen, surpassing the market’s earlier projection of 760 billion yen.

Highlighting the unprecedented nature of this subsidy, Amari underscores the imperative of ensuring companies’ operational profitability. Japan envisions becoming a pivotal player in the semiconductor supply chain. Furthermore, contingent on the development scenario, the government is committed to evaluating subsidy reductions, with a pledge to support various schemes for establishing Japan as a long-term semiconductor hub.

As of now, the construction of TSMC’s first-phase fab in Kumamoto is advancing rapidly, with the total workforce anticipated to surpass a thousand. The team is preparing for a timely production launch in 2024.

Although the Kumamoto fab’s announcement and construction preceded that of the U.S. Arizona fab, set to commence production in 2025, TSMC’s Kumamoto fab is garnering robust support from official Japanese channels and partners including SONY Semiconductor Solutions and Denso. The fab is set to utilize 22/28 nm and 12/16 nm processes, with a total capital expenditure of 8.6 billion USD. The Japanese Ministry of Economy, Trade and Industry(METI) granted approval for a subsidy of 476 billion yen in June 2022, which represents approximately 40% of total capital expenditure is supported by the subsidy.

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NVIDIA and Intel are adapting to the latest U.S. chip export restrictions by introducing downgraded AI chips specifically tailored for the Chinese market, UDN News said.

According to insider from the China Star Market, a Chinese media, NVIDIA has developed three downgraded AI chip models for the Chinese market. Intel also plans to release downgraded Gaudi 2 chip with an aim to US restriction.

NVIDIA’s latest downgraded AI chips, including HGX H20, L20 PCle, and L2 PCle, are anticipated to be unveiled after November 16th. Chinese companies are likely to receive samples in the coming days. These three chips, derived from the modification of NVIDIA H100, will align their performance with parameters below the new U.S. regulations. Ongoing communication with NVIDIA suggests mass production is slated for the year-end, said by industry sources.

Besides, Yicai also confirms from multiple NVIDIA supply chain sources. The three AI chip products are designed for cloud training, cloud inference, and edge inference, with specific launch times pending confirmation. Sampling is projected between November and December this year, followed by mass production from December this year to January next year.

On the Intel front, there are rumors of a response plan. As reported by The Paper, Intel is planning to release an improved version of its Gaudi 2 chip. Although the rumor exists, specific details are yet to be disclosed.

Since the U.S. government introduced chip export control to China last year, NVIDIA initially designed downgraded AI chips A800 and H800 for Chinese companies. However, new regulations in October this year by the U.S. Department of Commerce brought A800, H800, L40S, and other chips under control. Failure to secure export permission may necessitate order cancellations for NVIDIA.

(Image: Nvidia)