According to media reports, in response to the booming demand in the artificial intelligence market, TSMC has altered its Kaohsiung factory plan. Originally scheduled for a 28-nanometer mature process, the factory will now be equipped with a 2-nanometer advanced process, with mass production expected to commence in the latter half of 2025. The official announcement of this factory plan is imminent.

During a investor conference held on July 20th, TSMC refrained from making any comments, citing the current quiet period. As reported by “Central News Agency,” Kaohsiung Mayor Chen Chi-mai expressed the city government’s respect for TSMC and pledged full assistance. However, it is worth noting that the 2-nanometer process requires more funding compared to the 28-nanometer process, and TSMC has already informed the Kaohsiung city government, seeking support in terms of water and power supply.

Official data indicates that TSMC’s 2-nanometer process offers a 10% to 15% performance improvement at the same power consumption or a 20% to 30% reduction in power consumption at the same performance level compared to the 3-nanometer process. The primary production base for the 2-nanometer process will be located in Hsinchu’s Baoshan area, with plans to construct four fabs. The trial production is scheduled for 2024, followed by mass production in the latter half of 2025.

(Photo credit: TSMC)

In the continued sluggish consumer electronics market and amidst the booming era of artificial intelligence, semiconductor manufacturers are actively targeting high-performance chips and intensifying the competition over the 2nm process node.

TSMC, Samsung, and the newcomer Rapidus are all actively positioning themselves in the 2nm chip race. Let’s take a look at the progress of these three enterprises.

TSMC: Roadmap for 3nm and 2nm Unveiled

TSMC believes that, at the same power level, the 2nm (N2) chip speed can increase by 15% compared to N3E, or reduce power consumption by 30%, with a density 1.15 times that of its predecessor.

TSMC’s current roadmap for the 3nm “family” includes N3, N3E, N3P, N3X, and N3 AE. N3 is the basic version, N3E is an improved version with further cost optimization, N3P offers enhanced performance, planned for production in the second half of 2024, N3X focuses on high-performance computing devices, and aims for mass production in 2025. N3 AE, designed for the automotive sector, boasts greater reliability and is expected to help customers shorten their product time-to-market by 2 to 3 years.

As for 2nm, TSMC foresees the N2 process to enter mass production in 2025. Media reports from June this year indicate that TSMC is fully committed and has already commenced pre-production work for 2nm chips. In July, the TSMC supply chain revealed that the company has informed equipment suppliers to start delivering 2nm-related machines in the third quarter of next year.

Samsung Electronics: 2nm Mass Production by 2025

In June this year, Samsung announced its latest foundry technology innovations and business strategies.

Embracing the AI era, Samsung’s semiconductor foundry plans to leverage GAA advanced process technology to provide robust support for AI applications. To achieve this, Samsung unveiled detailed plans and performance levels for 2nm process mass production. They aim to realize the application of 2nm process in the mobile sector by 2025, expanding to HPC and automotive electronics in 2026 and 2027, respectively.

Samsung states that the 2nm process (SF2) offers a 12% performance improvement and 25% power efficiency increase over the 3nm process (SF3), with a 5% reduction in chip area.

Rapidus: 2nm Chip Making Progress

Established in November 2022, Rapidus gained significant attention as eight major Japanese companies, including Sony Group, Toyota Motor, SoftBank, Kioxia, Denso, NTT, NEC and MUFG jointly announced their investment in the company. Just a month after its founding, Rapidus forged a strategic partnership with IBM to jointly develop 2nm chip manufacturing technology.

According to Rapidus’ plans, 2nm chips are set to begin trial production in 2025, with mass production commencing in 2027.

[Update] Intel: Being Ambitious to Start Mass Production Of Its 20A Process in The First Half of 2024

Intel is making a vigorous stride into the semiconductor foundry market, setting its sights on rivals like TSMC and Samsung in the arena of advanced process technologies. Intel’s ambitious road map includes kick-starting mass production of its 20A process in the first half of 2024, followed by an 18A process rollout in 2H24. TrendForce points out, however, Intel has a number of significant hurdles to overcome:

Intel’s longstanding focus on manufacturing CPUs, GPUs, FPGAs, and associated I/O chipsets leaves it short of the specialized processes mastered by other foundries. Therefore, the potential success of Intel’s acquisition of Tower—a move to broaden its product line and market reach—is a matter of crucial importance.

Beyond financial segregation, the division of Intel’s actual manufacturing capabilities poses a pivotal challenge. It remains to be seen whether Intel can emulate the complete separation models like those of AMD/GlobalFoundries or Samsung LSI/Samsung Foundry, staying true to the foundry principle of not competing with clients. Adding complexity to the mix, Intel faces the potential exodus of orders from a key customer—its own design division.

(Photo credit: TSMC)

According to sources cited by Nikkan Kogyo Shimbun, TSMC intends to commence the construction of the second fab in Kikuyo-cho, Kumamoto Prefecture, Japan, in April 2024, with the goal of commencing production before the end of 2026.

It is worth mentioning that news about TSMC’s plan to build its second fab in Japan had already surfaced earlier this year. In January, TSMC’s CEO, CC Wei, revealed that the company was considering establishing a second chip manufacturing facility in Japan. In June, TSMC’s Chairman, Mark Liu, also mentioned during a shareholders’ meeting that the Japanese government expressed a desire for TSMC to continue expanding its investments in Japan, while TSMC was still evaluating the construction of the second fab in the country.

Regarding TSMC’s establishment of a fab in Japan, TrendForce indicated that TSMC has played an instrumental role in fostering the growth of Japan’s semiconductor industry as Japanese fabs are unable to handle manufacturing processes as advanced as 1Xnm. TrendForce posits that TSMC could potentially consider setting up a 7nm production line in Phase 2 of JASM to cater to Japan’s demand for advanced technology. Yet, the ongoing market slowdown necessitates a long-term appraisal before implementing any expansion strategies.

In addition to TSMC, more than 20 new wafer fabs are scheduled for completion in the coming years, despite the industry being in a downturn. According to TrendForce’s statistics report in January this year, there are over 20 planned new wafer fabs worldwide, including 5 in Taiwan, 5 in the United States, 6 in Mainland China, 4 in Europe, and 4 in Japan, South Korea, and Singapore combined.

Furthermore, numerous new wafer fab projects have been announced globally since the beginning of this year. For example, in February, Infineon and Texas Instruments both announced plans to construct new wafer fabs. Infineon plans to invest 5 billion euros to build a 12-inch wafer fab in Germany, while Texas Instruments intends to establish its second 300mm wafer fab in Lehi, Utah, USA. On July 5th, PSMC signed an agreement with SBI of Japan, proposing the establishment of a 12-inch wafer foundry.

Currently, semiconductor resources have become strategic assets. In addition to considering commercial and cost structures, wafer fabs must also account for government subsidy policies, meet customer demands for local production, and maintain supply-demand balance. TrendForce believes that future product diversity and pricing strategies will be key factors for the operation of wafer fabs.

TrendForce has released the latest spot prices of memory, which have continued to decline due to the impact of the stagnant market conditions. Both DRAM and NAND Flash spot prices have dropped further. The details are as follows:

DRAM Spot Market:

Compared with last week, the spot market is still not showing a noticeable improvement in terms of trading activities. Sellers are under a certain amount of pressure because some module houses have already stocked up in advance, and the demand from channels remains fairly weak. Hence, spot prices of DDR4 and DDR5 products continue to register daily drops. The average spot price of the mainstream chips (i.e., DDR4 1Gx8 2666MT/s) fell by 0.27% from US$1.501 last week to US$1.497 this week.

NAND Flash Spot Market:

There has been no apparent WoW improvement to the dynamics of the NAND Flash spot market this week. Several module houses, having elevated their inventory in advance, are now experiencing a certain extent of sales pressure from a lack of betterment in demand among channel markets, which led to an on-going drop of NAND Flash prices. 512Gb TLC wafer spots have dropped by 0.28% this week, arriving at US$1.404.

AI Chips and High-Performance Computing (HPC) have been continuously shaking up the entire supply chain, with CoWoS packaging technology being the latest area to experience the tremors.

In the previous piece, “HBM and 2.5D Packaging: the Essential Backbone Behind AI Server,” we discovered that the leading AI chip players, Nvidia and AMD, have been dedicated users of TSMC’s CoWoS technology. Much of the groundbreaking tech used in their flagship product series – such as Nvidia’s A100 and H100, and AMD’s Instinct MI250X and MI300 – have their roots in TSMC’s CoWoS tech.

However, with AI’s exponential growth, chip demand from not just Nvidia and AMD has skyrocketed, but other giants like Google and Amazon are also catching up in the AI field, bringing an onslaught of chip demand. The surge of orders is already testing the limits of TSMC’s CoWoS capacity. While TSMC is planning to increase its production in the latter half of 2023, there’s a snag – the lead time of the packaging equipment is proving to be a bottleneck, severely curtailing the pace of this necessary capacity expansion.

Nvidia Shakes the foundation of the CoWoS Supply Chain

In these times of booming demand, maintaining a stable supply is viewed as the primary goal for chipmakers, including Nvidia. While TSMC is struggling to keep up with customer needs, other chipmakers are starting to tweak their outsourcing strategies, moving towards a more diversified supply chain model. This shift is now opening opportunities for other foundries and OSATs.

Interestingly, in this reshuffling of the supply chain, UMC (United Microelectronics Corporation) is reportedly becoming one of Nvidia’s key partners in the interposer sector for the first time, with plans for capacity expansion on the horizon.

From a technical viewpoint, interposer has always been the cornerstone of TSMC’s CoWoS process and technology progression. As the interposer area enlarges, it allows for more memory stack particles and core components to be integrated. This is crucial for increasingly complex multi-chip designs, underscoring Nvidia’s intention to support UMC as a backup resource to safeguard supply continuity.

Meanwhile, as Nvidia secures production capacity, it is observed that the two leading OSAT companies, Amkor and SPIL (as part of ASE), are establishing themselves in the Chip-on-Wafer (CoW) and Wafer-on-Substrate (WoS) processes.

The ASE Group is no stranger to the 2.5D packaging arena. It unveiled its proprietary 2.5D packaging tech as early as 2017, a technology capable of integrating core computational elements and High Bandwidth Memory (HBM) onto the silicon interposer. This approach was once utilized in AMD’s MI200 series server GPU. Also under the ASE Group umbrella, SPIL boasts unique Fan-Out Embedded Bridge (FO-EB) technology. Bypassing silicon interposers, the platform leverages silicon bridges and redistribution layers (RDL) for integration, which provides ASE another competitive edge.

Could Samsung’s Turnkey Service Break New Ground?

In the shifting landscape of the supply chain, the Samsung Device Solutions division’s turnkey service, spanning from foundry operations to Advanced Package (AVP), stands out as an emerging player that can’t be ignored.

After its 2018 split, Samsung Foundry started taking orders beyond System LSI for business stability. In 2023, the AVP department, initially serving Samsung’s memory and foundry businesses, has also expanded its reach to external clients.

Our research indicates that Samsung’s AVP division is making aggressive strides into the AI field. Currently in active talks with key customers in the U.S. and China, Samsung is positioning its foundry-to-packaging turnkey solutions and standalone advanced packaging processes as viable, mature options.

In terms of technology roadmap, Samsung has invested significantly in 2.5D packaging R&D. Mirroring TSMC, the company launched two 2.5D packaging technologies in 2021: the I-Cube4, capable of integrating four HBM stacks and one core component onto a silicon interposer, and the H-Cube, designed to extend packaging area by integrating HDI PCB beneath the ABF substrate, primarily for designs incorporating six or more HBM stack particles.

Besides, recognizing Japan’s dominance in packaging materials and technologies, Samsung recently launched a R&D center there to swiftly upscale its AVP business.

Given all these circumstances, it seems to be only a matter of time before Samsung carves out its own significant share in the AI chip market. Despite TSMC’s industry dominance and pivotal role in AI chip advancements, the rising demand for advanced packaging is set to undeniably reshape supply chain dynamics and the future of the semiconductor industry.

(Source: Nvidia)