According to Economic Daily News, industry insiders said that Vanguard International Semiconductor (VIS) is in talks to acquire land and facilities from AUO’s Singapore plant for its first 12-inch fab. The estimated investment for this project is a substantial US$2 billion. VIS is making a strategic move to specialize in producing advanced chips for the automotive industry.

AUO is scheduled to hold a conference on October 31st, and VIS will follow suit on November 7th. Both companies are currently in a pre-conference quite period and haven’t made any official comments on the recent rumors.

Per reports, AUO has been gradually relocating its equipment from its Singapore plant back to Taiwan. Following a model where AUO sold its L3B fab and related facilities in Hsinchu Science Park, Taiwan, they plan to sell this Singapore plant to VIS. Notably, this Singapore plant is conveniently located just an eight-minute drive away from TSMC’s Singapore plant (SSMC), and the transaction is estimated to be worth over a billion dollars.

The Singapore plant in question was acquired by AUO in 2010, and it specializes in the production of 4.5th generation low-temperature polycrystalline silicon (LTPS) display panels and also has some capacity for AMOLED displays. However, the land use contract for this plant expired during the pandemic. AUO then redirected the plant’s focus towards supporting display production. However, with a decrease in post-pandemic notebook demand, AUO’s strategy in Singapore shifted from manufacturing to establishing itself as a regional service center.

Recent developments show that AUO has begun a significant production line adjustment.  They’re transforming the Longtan Aspire Park in Northern Taiwan into a hub for mass-producing Micro LED technology and integrated automotive display modules. Insiders suggest that AUO’s LTPS production line in the Singapore plant has already started moving to Longtan Aspire Park, where they’re gearing up for Micro LED technology development and eventual mass production.

Regarding AUO’s Singapore plant, the company recently stated that they are conducting a thorough evaluation of the operational efficiency of their various plants worldwide. The production schedule for the Singapore plant extends until early 2024, and they’ll subsequently assess the equipment and assets. The company is in the process of discussing and evaluating the related strategies, and they haven’t made any final decisions yet. AUO’s Singapore plant employs approximately 500 people, and they are committed to following local regulations to safeguard their employees’ rights.

In an earning calls last year, Chairman of VIS, Leuh Fang, revealed that the company already operates five 8-inch fabs. Fab 5 still has the potential for increased wafer production, but due to the challenges of acquiring new 8-inch equipment, establishing a brand-new 12-inch fab in Singapore makes more sense if customer demand necessitates capacity expansion.

This development isn’t entirely surprising, as there’s a precedent for fab transactions between AUO and VIS. In late April 2021, AUO sold its L3B plant in the Hsinchu Science Park, along with its related equipment, to VIS for NT$905 million (pre-tax).
(Image: AUO)

Escalating demand in sectors like electric vehicles, 5G communications, photovoltaics, and memory storage is currently fueling the rapid growth of the silicon carbide (SiC) industry. Key players in China are intensifying their research and development efforts to overcome technological challenges and secure a substantial market share.

The arrival of 8-inch SiC substrates is crucial and marks a technological significant milestone that everyone desires, opening up new possibilities.

The Turning Point: 8-Inch SiC Substrates

As a third-generation semiconductor material, SiC boasts advantages like a wider bandgap, higher breakdown electric field, and exceptional thermal conductivity. Its stellar performance in high-temperature, high-pressure, and high-frequency applications positions it as a cornerstone in the realm of semiconductor materials.

Fueled by growing demand downstream, the SiC industry is in the midst of a high-speed expansion phase. TrendForce’s analysis forecasts the SiC power device market to reach US$2.28 billion in 2023, with an impressive annual growth rate of 41.4%. By 2026, this market is expected to expand further, reaching US$5.33 billion.

From an industry perspective, SiC devices’ cost structure encompasses substrates, epitaxy, tape out, and packaging processes, with substrates accounting for a substantial 45% of total production costs. To reduce per-device costs, the strategy revolves around enlarging SiC substrates and increasing the number of die per substrate. Notably, 8-inch SiC substrates offer distinct cost advantages over their 6-inch counterparts.

Data from Wolfspeed reveals that the transition from 6-inch to 8-inch substrates results in a modest increase in processing costs but yields an impressive 80-90% increase in the production of qualified chips. The greater thickness of 8-inch substrates helps maintain the shape during processing, reduces edge curvature, and minimizes defect density. Consequently, adopting 8-inch substrates can lead to a substantial 50% reduction in unit production costs.

According to TrendForce’s analysis, the SiC industry currently centers around 6-inch substrates, holding an impressive 80% market share, while 8-inch substrates account for only 1%. The transition to larger 8-inch wafers represents a crucial strategy to further reduce SiC device costs. As 8-inch wafers mature, their pricing is expected to be about 1.5 times that of 6-inch wafers, while producing approximately 1.8 times dies compare with 6-inch SiC wafers, greatly improving wafer utilization.

The industry is steadfastly progressing from 6-inch to 8-inch substrates, offering Chinese manufacturers a unique opportunity to surge ahead. TrendForce’s data suggests that the current market share of 8-inch products stands at less than 2%, with a projected growth to approximately 15% by 2026.

Seizing the Moment: Advancing 8-Inch SiC Substrates

Industry experts highlight the dual challenges of growing 8-inch SiC crystals: (1) the development of 8-inch seed crystals and (2) temperature field uniformity, gas-phase material distribution, transportation efficiency, and increased stress leading to crystal cracking.

As per industry insiders, 2023 is poised to become the “Year of 8-Inch SiC.” Throughout the year, global power semiconductor giants like Wolfspeed and STMicroelectronics have accelerated their efforts to develop 8-inch SiC. In China, significant breakthroughs have been achieved in SiC equipment, substrates, and epitaxy segments, with numerous industry leaders forming alliances with international power semiconductor giants.

TrendForce’s data from the Compound Semiconductor Market reveal that 10 enterprises and institutions in China are currently advancing the development of 8-inch silicon carbide (SiC) substrates. These include Semisic, JSG, SICC, Summit Crystal, Synlight, Institute of Physics Chinese Academy of Sciences, Shandong University, TankeBlue, KY Semiconductor, and IV-Semitec.

Here are the list of Chinese companies in the 8-inch SiC substrate field this year:

KY Semiconductor:

• April 2023: Successfully completed the 8-inch SiC pilot line.
• June 2023: Achieved an average crystal growth yield of over 50% in the 8-inch SiC pilot line with crystal thickness exceeding 15mm.
• September 2023: Successfully launched the 8-inch SiC substrate processing workshop.

IV-Semitec:

• May 2023: Grew 8-inch n-type silicon carbide ingots with a thickness of 27 millimeters.
• September 2023: Signed a strategic cooperation agreement with Spectrum Semiconductor and Gietsic for the joint development of SiC-related products.
• October 2023: Commenced the construction of the pilot line for SiC substrates, with an annual production capacity of 600,000 pieces of 6-8 inch SiC substrates.

Summit Crystal:

• June 2023: Opened the Jinan’s Base with a planned production capacity of 500,000 pieces. It aims to reach full production by 2025, with an expected output value exceeding 5 billion RMB.
• August 2023: Cooperated with Shangdong University, successfully manufactured 8-inch SiC wafers the threading screw dislocation (TSD) density was 0.55 cm^-2, and the basal plane dislocation (BPD) density was 202 cm^-2.

Hoshine Silicon:

• May 2023: Successfully achieved the development and mass production of 8-inch silicon carbide substrates.
• October 2023: 20,000 SiC substrates passed acceptance inspection, demonstrating the capability for mass production.

Synlight:

• September 2021: Launched the single crystal silicon carbide growth project with plans to achieve an annual production capacity of 100,000 pieces upon reaching full production.
• April 2023: Successfully developed 8-inch silicon carbide crystal samples and plans to start small-scale production by the end of the year.

TankeBlue:

• January 2023: Successfully prepared 4H-SiC single crystals with a diameter of 209 mm using the physical vapor transport (PVT) method and produced standard 8-inch SiC single crystal substrates.
• May 2023: Signed a supply agreement with Infineon and started supplying silicon carbide materials.
• August 2023: Began construction of the second-phase expansion project, planning to increase capacity by 160,000 pieces.

JSG:

• June 2023: Successfully developed 8-inch single-wafer silicon carbide epitaxial growth equipment compatible with 6 and 8 inch silicon carbide epitaxial production.
• October 2023: Achieved independent development and commissioning of 8-inch single-wafer silicon carbide epitaxial growth equipment with thickness uniformity within 1.5% and dopant uniformity within 4%.

SanAn Optoelectronics:

• Established a joint venture with STMicroelectronics to build an 8-inch silicon carbide device manufacturing plant, which is expected to start production in the fourth quarter of 2025.
• September 2023: Announced the 8-inch silicon carbide substrate with a production capacity of 12,000 pieces per month, and silicon-based gallium nitride capacity of 2,000 pieces per month.
• October 2023: Started small-scale production and sampling of 8-inch silicon carbide substrates using low-cost technology with low defect density.

SICC:

• May 2023: Signed a new substrate and ingot supply agreement with Infineon, planning to transition to 8-inch silicon carbide wafers.
• June 2023: Successfully prepared low-defect 8-inch silicon carbide crystals with a thickness exceeding 60mm.

At this year’s Qualcomm Snapdragon Summit, the company announced its latest PC processor, the Snapdragon X Elite. With impressive performance metrics, this development is poised to shake up the PC processor market as Arm architecture gains ground, posing a substantial challenge to the established x86 architecture.

At this year’s Qualcomm Snapdragon Summit, the company announced its latest PC processor, the Snapdragon X Elite. The launch of laptops featuring the Qualcomm Snapdragon X Elite is expected in mid-2024, marking an opportune moment for a “counteroffensive.”

TrendForce indicates that Arm architecture PC processors have secured around an 11% market share this year, primarily propped up by Apple’s laptop processors. Industry insiders reveal that, in light of the growth potential in the PC processor market, semiconductor giants are increasingly adopting ARM architecture to venture into the market.

2024 Sees Laptop Upgrade Surge, Desktop Market Shrinks                  

Statistics reveal that the surge in remote work during 2020 prompted a shift in consumer preferences from desktop computers to laptops. Moreover, the ongoing establishment of cloud platforms by businesses in 2021 and 2022 has generated positive momentum, signaling a shrinking desktop market and an expanding PC market.

AI-powered PCs and Windows 12 next year are expected to ride a fresh wave of upgrades in 2024. Therefore, when PCs featuring ARM architecture become widespread, Intel and AMD may not be predominantly affected in the laptop processor business based on the x86 architecture. Instead, the desktop processor segment could face the most significant impact.

Kedar Kondap, Qualcomm’s Senior Vice President and General Manager of the Compute and Games Division, foresees an upgrade wave fueled by AI PCs next year, with further growth anticipated in 2025. It is expected that consumers will lean towards AI PCs for their next computer purchases.

The initial wave of products equipped with Qualcomm’s AI PC processors has been unveiled, aligning with the upcoming wave of device upgrades in next year. While Intel is set to launch its first AI acceleration engine, the Intel Core Ultra, featuring integrated NPU in December, its Microsoft Windows 12 certification remains a point of observation.

In a broader perspective, Intel and AMD are positioned to follow up with the AI PC trend by 2025. This coincides with the ending service of Windows 10 and the gradual implementation of Wifi 7 and 6G technologies. By 2028, they are expected to play a pivotal role in driving AI PC growth.

On another note, a South Korean analyst anticipates that the growth momentum in AI PCs hinges on when Apple incorporates AI features into Mac computers.

ARM vs. x86, Microsoft’s Crucial Role                                    

This is because Microsoft is set to launch Windows 12 next year, featuring the built-in Copilot AI assistant. It will collaborate with operating systems and software such as Windows, Edge, Microsoft 365, Outlook, and the Bing search engine, ushering in an entirely new AI-driven user experience.

Several tech giants are fiercely competing in the AI PC market, with NVIDIA and AMD investing in the development of Arm architecture processors. It’s worth mentioning that in 2016, Microsoft agreed to let Qualcomm exclusively develop Windows-compatible chips, and this agreement is set to expire in 2024. Consequently, Qualcomm may gain a strategic advantage. In contrast, the collaboration between NVIDIA and MediaTek on Arm processors might only begin to bear fruit in 2025.

As for AMD’s foray into Arm architecture research and development, whether this indicates a less optimistic outlook for the x86 market is a matter for ongoing observation. Intel CEO Pat Gelsinger expressed that he isn’t concerned about Arm architecture processors vying in the PC market. From a different perspective, Intel may even consider assisting with manufacturing.

(Image: Qualcomm)

TSMC’s new plant in Kumamoto, Japan, is bustling. With more than a thousand employees hard at work, it is on track to commence mass production in 2024. This venture signifies TSMC’s commitment to meet customer demands and navigate geopolitical challenges by expanding its overseas production capabilities.

According to a report by Economic Daily, industry sources reveal that TSMC’s Kumamoto plant is making significant progress in terms of staffing. In August 2023, Taiwanese engineers arrived in Japan accompanied by their families. Simultaneously, locally recruited engineers have completed training and are being deployed to the Kumamoto plant in preparation for the 2024 production.

Notably, TSMC’s Kumamoto plant has successfully trained its workforce. When combined with local employees, the facility now boasts a workforce exceeding a thousand. For the latest Kumamoto plant updates, TSMC assures to refer to the information shared during the October 3Q23 earning conference.

In the prior conference, TSMC disclosed its construction of a cutting-edge wafer fab in Japan. This fab will employ 12/16 nm and 22/28 nm process technologies. TSMC has hired around 800 local employees, most of whom have gained valuable experience in Taiwan. Equipment installation began this month, and mass production is expected by late 2024 if all goes according to schedule.

TSMC’s Kumamoto plant is strongly supported by the Japanese government, Sony Semiconductor Solutions Corporation, Denso, and other partners. The plant’s total capital expenditure is $8.6 billion, and the Japanese Ministry of Economy, Trade and Industry approved a subsidy of 476 billion yen (about US$3.5 billion) in June, covering around 40% of the total Japanese subsidy amount.

The Japanese government is optimistic about TSMC introducing EUV lithography equipment for advanced process mass production in future plants. To secure TSMC’s expansion of the Kumamoto Plant, the government is intensifying its support, with discussions suggesting subsidies of up to 900 billion yen (about US$6.03 billion). This increase underscores Japan’s commitment to boosting domestic semiconductor production value, aligning with their 2030 goal. Companies like TSC, WAHLEE, and MA-tek are poised to expand in pursuit of this goal.

TSC established Shunkawa Co., Ltd. in Japan in 2022 and opened a Kumamoto office in August this year. TSC plans to closely monitor the evolution of new semiconductor plants and explore expansion opportunities in regions such as Tohoku and Hokkaido. Additionally, WAHLEE, a materials distributor, is actively partnering with original equipment manufacturers and Japanese trading companies to tap into the Japanese market.

(Image: TSMC)

As semiconductor manufacturing processes evolve more gradually, 3D packaging emerges as an effective means of prolonging Moore’s Law and enhancing the computational prowess of ICs. Within the realm of 3D stacking technology, the Interuniversity Microelectronics Centre (imec) based in Belgium categorizes 3D integration technologies into four distinct types, each determined by different partitioning locations within a chip: 3D-SIP, 3D-SIC, 3D-SOC, and 3D-IC. Based on our previous discussion of 3D-SIP and 3D-SIC stacking, this article places a spotlight on the other two technologies: 3D-SOC and 3D-IC.

Related Article: Differences Between 3D-SIP and 3D-SIC: Why Are TSMC, Intel, and Samsung All Actively Involved?

3D-SOC

A System on Chip (SOC) involves the redesign of several different chips, all fabricated using the same manufacturing process, and integrates them onto a single chip. 3D-SOC takes this concept to new heights by stacking multiple SOC chips vertically. The image below illustrates the transformation of a 2D System on Chip (2D-SOC), where circuits are redivided into blocks, and then stacked to form a 3D System on Chip (3D-SOC).

Source: imec

imec’s research team previously published a paper on IEEE, outlining the advantages of 3D-SOC and backside interconnects. This technology aims to achieve the integration of diverse chips in a heterogeneous system. By intelligently partitioning circuits, it significantly reduces power consumption and boosts computational performance. In comparison to the trending chiplet technology, 3D-SOC holds a competitive edge.

Eric Beyne, IMEC’s Vice President of Research and Project Director for 3D System Integration, pointed out, “Chiplets involve separately designed and processed chiplet dies. A well-known example are high-bandwidth memories (HBMs) – stacks of dynamic random access memory (DRAM) chips. This memory stack connects to a processor chip through interface buses, which limit their use to latency-tolerant applications. As such, the chiplet concept will never allow for fast access between logic and first and intermediate level cache memories.”

However, it’s essential to acknowledge that 3D-SOC technology comes with apparent drawbacks, primarily higher research and development costs and a longer development timeline compared to 3D-SIP technology. Nevertheless, as applications like AIGC, AR/VR, 8K, and others continue to drive the need for high-speed computing, chips are relentlessly progressing towards higher efficiency, lower power consumption, and smaller size. In this context, 3D-SOC technology will maintain its place in advanced packaging.

Backside Power Delivery Network (BSPDN)

The technology of Backside Power Delivery Network (BSPDN) represents a pivotal development in semiconductor manufacturing, offering several advantages, including more flexible circuit design, shorter metal wire lengths, and higher chip utilization. After transforming a 2D System on Chip (2D-SOC) into a 3D-SOC through layered stacking, the original back sides of the chips become the outer sides of the 3D-SOC. At this stage, the “freed-up” backside of the chips can be utilized for signal routing or as power lines for transistors, in contrast to traditional processes where wiring and power lines are designed on the front side of the wafer.

In the past, backside chips were merely used as carriers, but BSPDN technology allows for more space to be used for logic wafer design. According to simulation results, the transmission efficiency of backside PDN is seven times higher than traditional front-side PDN. Intel has also announced the introduction of this technology in the 20Å and 18Å processes.

To achieve BSPDN, a dedicated wafer thinning process (reducing it to a few hundred nanometers) is required, along with nanoscale through-silicon vias (nTSV) to connect backside power to the front-side logic chip.

Another key technology for BSPDN is the Buried Power Rail (BPR), a miniaturization technique that embeds wires beneath the transistors, with some inside the silicon substrate and others in shallow trench isolation oxide layers. BPR replaces power lines and ground lines under standard cells in traditional processes and further reduces the width of standard cells, mitigating IR voltage drop issues.

The diagram below illustrates BSPDN, where backside PDN’s metal wiring is connected to Buried Power Rails (BPR), and the backside of the chip (BS) is connected to the front side of the logic chip (FS).

Source: imec

3D-IC

The final category, 3D-IC, employs new 3D sequential technology (S3D) or Monolithic technology to vertically stack n-type and p-type transistors, forming a Complementary Field-Effect Transistor (CFET). This technology enables two transistors to be stacked and integrated into the size of a single transistor. This not only significantly increases transistor density but also simplifies the layout of CMOS logic circuits, enhancing design efficiency. As seen in the diagram below, n-type and p-type transistors are integrated vertically to form a CFET.

Source: imec

Nevertheless, the key challenge lies in how to vertically integrate each minuscule transistor and address heat dissipation issues under high-speed computing. Major manufacturers are still in the development phase, but the technology’s biggest advantage lies in achieving the highest component density and the smallest node width, even without nodes. With the continuous increase in demand for high-speed computing, 3D-IC technology is set to become a focal point in the industry’s development.

3D Stacking Leading the Global Semiconductor Advancement

imec has outlined a roadmap for 3D stacking, aiming to reduce pitch spacings and increase point density within unit areas. However, imec also emphasizes that the development of 3D packaging technologies does not follow a linear timeline, as depicted in the figure above, as there is no single packaging technology that can cater to all requirements.

With the rapid development of applications such as AIGC, AR/VR, 8K, 5G, and others, a significant demand for computing power is expected to persist. To overcome the bottlenecks in semiconductor process technology, countries worldwide are fully engaged in advanced packaging research, and 3D stacking undoubtedly takes the center stage as the elixir for Moore’s Law continuation.

Explore More

• An In-Depth Explanation of Advanced Packaging Technology: CoWoS
• Intel and Samsung Join TSMC in Fierce Advanced Packaging Race
• Continuing Moore’s Law: Advanced Packaging Enters the 3D Stacked CPU/GPU Era
• Understanding Chiplets, SoC, and SiP: Why TSMC, Intel, Samsung Invest?

(Image: Samsung)