Semiconductor process technology is nearing the boundaries of known physics. In order to continually enhance processor performance, the integration of small chips (chiplets) and heterogeneous Integration has become a prevailing trend. It is also regarded as a primary solution for extending Moore’s Law. Major industry players such as TSMC, Intel, Samsung, and others are vigorously developing these related technologies.

What are SoC, SiP, and Chiplet?

To understand Chiplet technology, we must first clarify two commonly used terms: SoC and SiP. SoC (System on Chip) involves redesigning multiple different chips to utilize the same manufacturing process and integrating them onto a single chip. On the other hand, SiP (System in Package) connects multiple chips with different manufacturing processes using heterogeneous integration techniques and integrates them within a single packaging form.

Chiplet technology employs advanced packaging techniques to create a SiP composed of multiple small chips. It integrates small chips with different functions onto a single substrate through advanced packaging techniques. While Chiplets and SiPs may seem similar, Chiplets are essentially chips themselves, whereas SiP refers to the packaging form. They have differences in functionality and purpose.

Chiplets: Today’s Semiconductor Development Trend

The design concept of Chiplet technology offers several advantages over SoC, notably in significantly improving chip manufacturing yield. As chip sizes increase to enhance performance, chip yield decreases due to the larger surface area. Chiplet technology can integrate various smaller chips with relatively high manufacturing yields, thus enhancing chip performance and yield.

Furthermore, Chiplet technology contributes to reduced design complexity and costs. Through heterogeneous integration, Chiplets can combine various types of small chips, reducing integration challenges in the initial design phase and facilitating design and testing. Additionally, since different Chiplets can be independently optimized, the final integrated product often achieves better overall performance.

Chiplets have the potential to lower wafer manufacturing costs. Apart from CPUs and GPUs, other units within chips can perform well without relying on advanced processes. Chiplets enable different functional small chips to use the most suitable manufacturing process, contributing to cost reduction.

With the evolution of semiconductor processes, chip design has become more challenging and complex, leading to rising design costs. In this context, Chiplet technology, which simplifies design and manufacturing processes, effectively enhances chip performance, and extends Moore’s Law, holds significant promise.

Applications and Development of Chiplets

In recent years, global semiconductor giants like AMD, TSMC, Intel, NVIDIA, and others have recognized the market potential in this field, intensively investing in Chiplet technology. For example, AMD’s recent products have benefited from the ‘SiP + Chiplet’ manufacturing approach. Moreover, Apple’s M1 Ultra chip achieved high performance through a customed UltraFusion packaging architecture. In academia, institutions like the University of California, Georgia Tech, and European research organizations have begun researching interconnect interfaces, packaging, and applications related to Chiplet technology.

In conclusion, due to Chiplet technology’s ability to lower design costs, reduce development time, enhance design flexibility and yield, while expanding chip functionality, it is an indispensable solution in the ongoing development of high-performance chips.

This article is from TechNews, a collaborative media partner of TrendForce.

According to a report by Taiwan’s TechNews, the Huawei Kirin 9000S mobile processor, dubbed by Chinese media as “4G technology with 5G speed,” was incorporated into the Huawei Mate 60 Pro smartphone on the 29th. The phone was made available for purchase directly without a launch event or prior promotion, priced at 6,999 Chinese Yuan, sparking significant industry discussion.

The discussion around the Huawei Kirin 9000S mobile processor stems from the fact that, for the first time post the US-China trade war, a chip foundry has manufactured chips for Huawei, featuring an advanced 5-nanometer process. Does this signify a breakthrough for Chinese chip production amidst US restrictions and a leap forward in China’s semiconductor industry? At present, the answer seems to be negative.

According to insiders’ revelations, the Mate 60 Pro’s Kirin 9000S chip was manufactured by SMIC. However, key production aspects are still under US control, making breaking through these limitations quite challenging.

Screenshots shared by users indicate that Kirin is on a 5nm process. Nonetheless, technical experts widely believe that the 9000S isn’t on a 5nm process; rather, it’s on SMIC’s N+2 process.

Source: fin

SMIC is the only Chinese enterprise capable of mass-producing 14-nanometer FinFET technology. Both N+1 and N+2 processes are improvements based on the 14nm FinFET technology and are achieved through DUV lithography, bypassing US restrictions. (The most advanced processes currently require EUV lithography machines.)

SMIC has not openly stated that N+1 and N+2 are on the 7nm process. However, the chip industry generally considers N+1 to be equivalent to 7nm LPE (Low Power) technology, and N+2 to be equivalent to 7nm LPP (High Performance) technology. The shipment of the Mate 60 Pro seems to have openly revealed information about SMIC’s N+2 process reaching maturity and entering mass production.

(Photo credit: Huawei)

DRAM Spot Market
Spot prices of DRAM products have risen slightly lately due to Samsung’s earlier attempt to raise prices of 3D NAND Flash wafers as well as the temporary halt in the flow of rebelled used chips into the market. DDR4 products have experienced a more noticeable price increase compared with DDR5 products. However, there is still insufficient actual demand to sustain the rise in spot prices. Furthermore, most spot traders already have sufficient inventory. Therefore, prices have stopped falling, but the overall transaction volume is not expanding. TrendForce believes spot prices are near the trough for this downturn phase of the price cycle. Nevertheless, there is some time before the overall average spot will rebound because demand visibility is limited. The average spot price of the mainstream chips (i.e., DDR4 1Gx8 2666MT/s) fell by 0.34% from US$1.456 last week to US$1.451 this week.

NAND Flash Spot Market
The intermittent price increases of packaged dies at various capacities are reflecting persistently sluggish market demand, while wafer prices, after several consecutive weeks of elevation in prices, are now gradually subsiding in differences to that of the contract market. 512Gb TLC wafer spots have risen by 3.88% this week, arriving at US$1.578.

According to Taiwan’s TechNews report, Intel has revealed the architecture and supply schedule of the new generation data center Xeon processors, Sierra Forest and Granite Rapids. They are also set to unveil the consumer processor codenamed Meteor Lake in mid-September. However, with the semiconductor market’s current weak recovery, the impact of Intel’s new processors on driving upgrades and benefiting Taiwanese supply chain manufacturers remains uncertain, making it a market focal point.

Regarding the consumer-oriented Meteor Lake processor, industry sources suggest that it will not only be the first to adopt “Intel 4” technology, but also the first to utilize EUV lithography for cost reduction in mass-producing CPU tiles. TSMC will assist in production using the 5/6 nanometer process for graphics chip modules (GFX tile), system chip modules (SoC tile), and input/output chip modules (IOE tile), aiming for higher yields to decrease production costs.

Furthermore, the Meteor Lake processor shifts from traditional monolithic chip design to chiplet technology. After separating functions like graphics, system, and I/O chips, it employs the 3D Foveros advanced packaging technology. Through Foveros interconnects, multiple chiplets are vertically stacked into one chip. This approach not only increases the yield of critical modules but also reduces costs, granting Intel greater flexibility in rapidly creating next-generation chip capacities.

For the upcoming Meteor Lake processor, its direct beneficiary is undoubtedly TSMC, which assists in producing graphics chip modules, system chip modules, and input/output chip modules using the 5/6 nanometer process. This collaboration not only boosts revenue but also maintains the ongoing partnership with Intel.

However, despite Taiwanese foundries and board manufacturers securing orders for Intel’s new-generation processors, the current economic environment remains unfavorable. With a cautious and conservative outlook on consumer spending in the global market, the launch of Intel’s new products could either boost supply chain revenue or lead to increased inventory in the next phase, requiring further observation.

(Photo credit: Intel)

According to a report from Taiwan’s TechNews, NVIDIA has delivered impressive results in its latest financial report, coupled with an optimistic outlook for its financial projections. This demonstrates that the demand for AI remains robust for the coming quarters. Currently, NVIDIA’s H100 and A100 chips both utilize TSMC’s CoWoS advanced packaging technology, making TSMC’s production capacity a crucial factor.

Examining the core GPU market, NVIDIA holds a dominant market share of 90%, while AMD accounts for about 10%. While other companies might adopt Google’s TPU or develop customized chips, they currently lack significant operational cost advantages.

In the short term, the shortage of CoWoS has led to tight chip supplies. However, according to a recent report by Morgan Stanley Securities, NVIDIA believes that TSMC’s CoWoS capacity won’t restrict shipments of the next quarter’s H100 GPUs. The company anticipates an increase in supply for each quarter next year. Simultaneously, TSMC is raising CoWoS prices by 20% for rush orders, indicating that the anticipated CoWoS bottleneck might alleviate.

According to industry sources, NVIDIA is actively diversifying its CoWoS supply chain away from TSMC. UMC, ASE, Amkor, and SPIL are significant players in this effort. Currently, UMC is expanding its interposer production capacity, aiming to double its capacity to relieve the tight CoWoS supply situation.

According to Morgan Stanley Securities, TSMC’s monthly CoWoS capacity this year is around 11,000 wafers, projected to reach 25,000 wafers by the end of next year. Non-TSMC CoWoS supply chain’s monthly capacity can reach 3,000 wafers, with a planned increase to 5,000 wafers by the end of next year.

(Photo credit: TSMC)