According to The Register, Fujitsu and Supermicro are teaming up to develop a new platform featuring Fujitsu’s upcoming high-performance, Arm-based MONAKA processor and advanced liquid cooling systems.

On October 3, Fujitsu and Supermicro announced a long-term partnership to develop and market a platform using the FUJITSU-MONAKA processor, which is designed for high performance and energy efficiency and set to launch in 2027. The companies will also collaborate on liquid-cooled systems for high-performance computing (HPC), generative AI, and eco-friendly data centers.

The Register highlights two key aspects of the alliance: Arm chips generally run cooler than competitors, requiring less thermal management innovation, and Fujitsu had largely exited this server market two years ago.

The Register reported that in February 2022, Fujitsu announced it would stop manufacturing and selling mainframe systems by 2030 and phase out Unix servers by the end of 2029. However, a year later, Fujitsu unveiled MONAKA, the successor to its A64FX chip, as a more energy-efficient, high-performance solution for HPC, AI, and data analytics workloads.

According to the companies, FUJITSU-MONAKA is based on the Arm architecture and employs cutting-edge 2-nanometer technology, with a 2027 release planned.

The partnership will combine Supermicro’s “Building Block” modular design, which allows customers to choose components optimized for their specific workloads, including cooling options like air-conditioned, free air cooled, or liquid cooling.

Fujitsu’s subsidiary, Fsas Technologies, will provide global generative AI solutions that integrate Supermicro’s GPU servers and support services for data centers and enterprises. Fsas was spun off last December to handle Fujitsu’s PC, server, and storage business, excluding mainframe and Unix systems.

The Register also mentioned that while liquid cooling for Arm systems is not common, it’s not unprecedented. For example, Fujitsu’s Fugaku supercomputer uses liquid cooling for its A64FX processors. This focus on liquid-cooled systems targets the growing demand for machines handling higher AI and HPC workloads.

(Photo credit: Supermicro)

As TSMC has reportedly begun trial production of 2nm chips in its Baoshan Plant in Hsinchu, northern Taiwan, the schedule of mass producing 2nm in 2025 remains on track. A report by Commercial Times reveals that the price of 2nm wafers is expected to double compared to 4/5nm, which may exceed USD 30,000 per wafer.

While the yield rates for advanced nodes of Intel and Samsung are rumored to be relatively low, the rising price of 2nm wafers reflects TSMC’s market monopoly as well as its strong pricing power, the report notes.

Citing comments by sources from semiconductor companies, the report states that fabs have invested heavily in advanced processes. For instance, the R&D investment of 3nm may exceed USD 4 billion, with key partners in TSMC’s supply chain, such as Taiwanese IP providers and material suppliers, playing a critical role.

On the other hand, executives from IC design houses cited by the report reveal that even from the perspective of IC design, the R&D cost for advanced nodes remains high. For instance, the development cost for 28nm is approximately USD 50 million, while 16nm may require an investment of USD 100 million. For 5nm, the R&D cost has soared to USD 550 million, if the expenditure on IP licensing, software verification, and design architecture are factored in.

According to the report, foundries have invested even more, with research institutions estimating that R&D expenses for 3nm may range from USD 4 billion to USD 5 billion. Additionally, constructing a 3nm fab is expected to cost at least USD 15 billion to USD 20 billion. All these factors may lead to the high pricing of wafers in the advanced nodes.

Therefore, for a foundry, the development of a new-generation of node involves massive efforts, and needed to be supported by partners in three key sectors: equipment, software (including IP and EDA tools), and materials, the report notes. Once their products have been validated by the foundry, suppliers can usually secure long-term partnership.

With 2nm set to debut in 2025, TSMC’s key suppliers are expected to see explosive profit growth, the report indicates. According to the report, Taiwanese IP firm M31, for example, has already developed IP that supports the 2nm platform for both smartphones and high-performance computing. Likewise, eMemory has disclosed that it is collaborating with leading foundries to develop 2nm.

On the other hand, as 2nm processes require thinner wafers, Taiwan-based materials companies, such as Kinik and Phoenix Silicon International Corp., have entered the markets of diamond discs and reclaimed wafers.

According to the report, in terms of reclaimed wafers, the market value for 2nm is approximately 4.6 times that of 28nm. In addition, the number of dummy wafers will also increase in advanced processes, which benefit suppliers with more volume and higher average prices.

Read more

• [News] TSMC Reportedly Mulls to Offer Discounts on Mature Nodes, Particular for 7nm/14nm Orders
• [News] TSMC’s Newly Acquired AP8 Facility in Southern Taiwan Rumored to Start Production in 2H25

(Photo credit: TSMC)

Amkor and TSMC announced today that the two companies have signed a memorandum of understanding to collaborate and bring advanced packaging and test capabilities to Arizona, further expanding the region’s semiconductor ecosystem.

Amkor and TSMC have been closely collaborating to deliver high volume, leading-edge technologies for advanced packaging and testing of semiconductors to support critical markets such as high-performance computing and communications. Under the agreement, TSMC will contract turnkey advanced packaging and test services from Amkor in their planned facility in Peoria, Arizona. TSMC will leverage these services to support its customers, particularly those using TSMC’s advanced wafer fabrication facilities in Phoenix. The close collaboration and proximity of TSMC’s front-end fab and Amkor’s back-end facility will accelerate overall product cycle times.

The companies will jointly define the specific packaging technologies, such as TSMC’s Integrated Fan-Out (InFO) and Chip on Wafer on Substrate (CoWoS) that will be employed to address common customers’ needs.

The agreement underscores the shared commitment to supporting customer requirements for geographic flexibility in front-end and back-end manufacturing, as well as fostering the development of a vibrant and comprehensive semiconductor manufacturing ecosystem in the United States. The companies’ shared vision is to enable seamless technology alignment for customers across a global manufacturing network.

“Amkor is proud to collaborate with TSMC to provide seamless integration of silicon manufacturing and packaging processes through an efficient turnkey advanced packaging and test business model in the United States,” said Giel Rutten, Amkor’s president and chief executive officer.

“Our customers are increasingly depending on advanced packaging technologies for their breakthroughs in advanced mobile applications, artificial intelligence and high-performance computing, and TSMC is pleased to work side by side with a trusted longtime strategic partner in Amkor to support them with a more diverse manufacturing footprint,” said Dr. Kevin Zhang, TSMC’s Senior Vice President of Business Development and Global Sales, and Deputy Co-COO.“We look forward to close collaboration with Amkor at their Peoria facility to maximize the value of our fabs in Phoenix and provide more comprehensive services to our customers in the
United States.”

(Photo credit: Amkor)

In addition to China, Russia has also made semiconductors one of its major focuses. According to a report by Tom’s Hardware, which cites local media CNews, the country has set aside over 240 billion rubles (USD 2.54 billion) to fund a program aimed at replacing 70% of the foreign chipmaking equipment by 2030.

This effort, according to the reports, includes the launch of 110 R&D projects to reduce reliance on imported wafer fabrication tools and eventually produce chips using 28nm-class process technology. However, it is worth noting that the total investment is 57 times smaller than what Russia plans to spend on defense in its war with Ukraine in 2025 alone, the reports note.

According to the reports, to put things in context, domestic chipmakers like Angstrem and Mikron can produce chips using mature technologies, such as 65nm and 90nm nodes. However, only 12% of the 400 tools used for chip production in the country are currently made locally.

Moreover, sanctions have worsened the situation, which raise the price of essential equipment by 40% to 50% due to the need to smuggle it into Russia, the reports indicate.

Therefore, to address these challenges, Russia’s Ministry of Industry and Trade, along with government-controlled MIET, have developed the initiative, which addresses multiple aspects of chipmaking, including manufacturing tools, raw materials, and electronic design automation (EDA) tools, according to the reports.

However, the report by Tom’s Hardware raises concerns about the feasibility of the initiative, as many of the specific details remain somewhat vague.

For instance, one of the initiative’s key goal is the development of lithography equipment for 350nm and 130nm process technologies, which has a very wide gap in between. Also, Russia intends to manufacture domestic lithography systems capable of handling 65nm and 90nm process technologies. Nevertheless, even this would represent significant progress in the country’s microelectronics production, it would still lag 25 to 28 years behind the industry’s leading edge, the report states.

Recently, Professor Xu Xiaohong and Professor Wang Fang from Shanxi Normal University, in collaboration with Researcher Xue Dingjiang from the Institute of Chemistry, Chinese Academy of Sciences, reported a template selection strategy for bottom-up synthesis of CrSbSe₃ nanoribbons.

They successfully achieved the controlled preparation of one-dimensional (1D) ferromagnetic CrSbSe₃ nanoribbons, which exhibit typical semiconductor behavior and ferromagnetism, confirming the intrinsic ferromagnetic properties of 1D CrSbSe₃ semiconductors.

With the rise of cloud computing technology, the scale and complexity of data storage have reached unprecedented levels, placing increasing demands on storage technologies. Magnetic semiconductors, as a new class of spintronic materials, hold the potential to simultaneously enable logic operations, information processing, and storage.

As a result, low-dimensional magnetic semiconductors have become an inevitable trend in the construction of nanoscale spintronic devices, aiming to minimize device size and achieve high-density integration. However, realizing such low-dimensional magnetic semiconductors remains challenging, especially for 1D ferromagnetic semiconductors with higher magnetic anisotropy, larger aspect ratios, and greater potential for nanoscale spintronic devices.

CrSbSe₃, as the only experimentally verified 1D material that possesses both ferromagnetic and semiconductor properties, is of significant importance in exploring its characteristics and applications. Until now, CrSbSe₃ nanocrystals could only be obtained through top-down exfoliation methods.

In response, the team reported a bottom-up solution method for synthesizing CrSbSe₃  nanoribbons. By comparing the formation energies of potential binary templates and ternary target products, they selected Sb2Se₃, a material with a 1D crystal structure, as the template. Half of the Sb atoms in Sb2Se₃ were replaced with Cr atoms, promoting the phase transition from Sb2Se₃ to CrSbSe₃. The synthesized CrSbSe₃ nanoribbons were approximately 5 µm in length, 80 to 120 nm in width, and about 5 nm thick. The nanoribbons exhibited soft magnetic behavior at temperatures below the Curie temperature of 71 K.

Magnetic and electrical tests conducted on individual CrSbSe₃ nanoribbons demonstrated their typical semiconductor behavior and ferromagnetism, further confirming the intrinsic ferromagnetic properties of the 1D CrSbSe₃ semiconductor. This work provides a novel bottom-up template synthesis method for ternary 1D nanoribbons, laying the foundation for the development and application of 1D ferromagnetic semiconductors.

(Photo credit: Shanxi Normal University)