TSMC’s fan-out (InFO) packaging process will no longer be exclusively used by Apple. According to a report from Commercial Times, it’s revealed that Google’s self-developed Tensor chips for their phones will switch to TSMC’s 3nm process next year and will also start using InFO packaging.

TSMC developed InFO packaging based on FOWLP (fan-out wafer-level packaging), which gained prominence after being adopted by the A10 processor in the iPhone 7 in 2016.

TSMC indicated that the current InFO_PoP technology has advanced to its ninth generation. Last year, it successfully certified 3nm chips, achieving higher efficiency and lower power consumption for mobile devices. The InFO_PoP technology, which features a backside redistribution layer (RDL), has entered mass production this year.

According to industry sources cited by the Commercial Times, Google will shift to TSMC for the Tensor G5 chips, which will be used in the Pixel 10 series next year. These chips will not only utilize the 3nm process but will also adopt integrated fan-out packaging.

This year’s Tensor G4 chips, set to be announced soon, use Samsung’s FOPLP (fan-out panel-level packaging). Although wafer-level packaging (WLP) is generally considered to have advantages over panel-level packaging (PLP), FOWLP still prevails at this stage due to yield and cost considerations.

TSMC has also begun developing FOPLP technology. Previously, per sources cited by a report from MoneyDJ, TSMC has officially formed a team, currently in the “Pathfinding” phase, and is planning to establish a mini line with a clear goal of advancing beyond traditional methods.

Although it is not expected to mature within the next three years, major customers like NVIDIA have partnered with foundry companies to develop new materials. One of TSMC’s major clients has already provided specifications for using glass materials.

Traditionally, chip advancements have been achieved through more advanced process nodes. However, new materials could enable the integration of more transistors on a single chip, achieving the same goal of scaling.

For instance, Intel plans to use glass substrates by 2030, potentially allowing a single chip to house one trillion transistors – 50 times the number in Apple’s A17 Pro processor. This suggests that glass substrates could become a significant milestone in chip development.

Another sources cited by Commercial Times have also indicated that glass substrates are part of the medium- to long-term technological roadmap. They can address challenges in large-size, high-density interconnect substrate development.

Currently, this technology is in the early stages of research and development. Its impact on ABF (Ajinomoto Build-up Film) substrates is expected to become significant in the second half of 2027 or later.

Read more

• [News] TSMC Pushes for FOPLP Mass Production by 2027, Reportedly Eyeing on Innolux’s Plant
• [News] TSMC Reportedly Forms a Team on FOPLP Development, with Mini Line on the Road

(Photo credit: TSMC)

According to STDaily citing a recent report on the official website of Okinawa Institute of Science and Technology Graduate University (OIST) in Japan announced that, the university has designed an extreme ultraviolet (EUV) lithography technology that surpasses the standard boundary of semiconductor manufacturing.

Lithography equipment based on such a design can use a smaller EUV light source, consuming less than one-tenth the power of traditional EUV lithography equipment, which can reduce costs and significantly improve the reliability and lifespan of the equipment.

In traditional optical systems, such as camera, telescope, and conventional ultraviolet lithography technologies, optical elements like apertures and lenses are arranged symmetrically along a straight axis. This method is not suitable for EUV rays because their wavelengths are extremely short and most will be absorbed by materials.

Thus, EUV light is guided using crescent-shaped mirrors, but this leads to light deviation from the central axis, sacrificing important optical properties and reducing the overall performance of the system.

To tackle this issue, the new lithography technology achieves its optical properties by aligning two axisymmetric mirrors with tiny central holes in a straight line. Due to the high absorption rate of EUV, each mirror reflection weakens the energy by 40%.

In accordance with industry standards, only about 1% of the EUV light source energy reaches the wafer after passing through 10 mirrors, which requires a very high EUV light output.

In contrast, limiting the number of mirrors from the EUV light source to the wafer to a total of four allows more than 10% of the energy to penetrate the wafer, which can largely bring down power consumption.

The core projector of the new EUV lithography technology, consisting of two mirrors similar to an astronomical telescope, can transfer the light mask image onto the silicon wafer. The team claims this configuration is incredibly simple since traditional projectors require at least six mirrors.

This was achieved by rethinking the theory of optical aberration calibration, and its performance has been verified by optical simulation software, which means it can meet the production requirements of advanced semiconductors.

Besides, the team designed a new type of illumination optical method called “dual-line field” for this novel technology, which uses EUV light to illuminate a plane mirror light mask from the front without interfering with the light path.

Read more

• [News] TSMC Reveals High-NA EUV Equipment Will Be Adopted at the Right Time
• [News] Price for ASML’s Hyper-NA EUV Rumored to Double, Causing TSMC, Samsung and Intel to Hesitate

(Photo credit: OIST)

A previous report from Economic Daily News once reported that, Innolux is set to sell its 4th Plant in Tainan (5.5-generation LCD panel plant), which was closed in 2023. Moreover, the report has cited rumors in the market, claiming that both Micron and TSMC have been actively exploring the acquisition.

Eariler on August 1st, the latest report from MoneyDJ further suggests that TSMC is almost certain to secure the deal, primarily to expand its CoWoS capacity. Regarding this matter, neither company has commented on these market rumors.

On July 30, Innolux announced its plan to dispose of the TAC plant-related real estate at the Southern Taiwan Science Park (STSP) D section, so as to bolster operational funds. To expedite the process and meet business needs, the board authorized Chairman Jim Hung to negotiate terms and sign relevant contracts with potential buyers.

Reportedly, the sale price must not be lower than the asset’s book value in the most recent financial statements, taking into account professional valuation reports and market information.

The recent trend of FOPLP (Fan-Out Panel Level Packaging) is said to have fueled speculation and discussions about Innolux’s plant sale, leading to rumors that TSMC is on the verge of announcing the purchase.

Yet, per MoneyDJ, TSMC’s current FOPLP applications in the AI field primarily involve stacking on rectangular substrates, integrating them into 2.5D and 3D packages. Initially, TSMC prefers to complete the entire FOPLP process in-house, integrating the front-end and back-end technologies of the 3D fabric platform.

For Innolux, besides gaining considerable non-operating income, this opportunity also raises the prospect of future collaboration.

Notably, this rumored move comes as construction at TSMC’s first P1 plant in the Southern Taiwan Science Park’s Chiayi Campus was halted due to the discovery of potential archaeological remains.

With P1 construction paused, TSMC has prioritized the construction of the second plant (P2). However, current capacity is very tight, and the time required to complete and ramp up P2 to mass production may not meet customer demand. The long-term substantial demand has driven TSMC to seek additional suitable locations in advance.

It is indicated by MoneyDJ that though TSMC’s Chiayi plant is currently facing delays due to the archaeological site issue, Chiayi is still planned to be a major hub for CoWoS production in the long term, with six phases planned. Previously, the company had considered expanding SoIC (System on Integrated Chips) production in Yunlin, but has recently decided to put those plans on hold.

Overall, the latest industry estimates suggest that CoWoS monthly capacity could reach about 35,000 to 40,000 wafers this year. On 2025, if outsourcing to packaging and testing subcontractors is included, capacity could potentially exceed 60,000 wafers, or even more next year.

Read more

• [News] Innolux Confirms Sale of Tainan Plant 4, with Micron & TSMC Reportedly in the Bidding Stage
• [News] TSMC Halts Chia-Yi Plant Construction Due to Relic Found, Quickly Initiates Preparation for 2nd Plant

(Photo credit: Innolux)

According to a report from Bloomberg, Jun Young-hyun, head of Samsung’s chip business, recently sent a stern warning to employees about the need to reform the company’s culture to avoid falling into a vicious cycle.

Jun stated that the recent improvement in Samsung’s performance was due to a rebound in the memory market. To sustain this progress, Samsung must take measures to eliminate communication barriers between departments and stop concealing or avoiding problems.

Earlier this week, Samsung announced its Q2 earnings, showcasing the fastest net profit growth since 2010. However, Jun Young-hyun highlighted several issues which may undermine Samsung’s long-term competitiveness.

He emphasized the need to rebuild the semiconductor division’s culture of vigorous debate, warning that relying solely on market recovery without restoring fundamental competitiveness would lead to a vicious cycle and repeating past mistakes.

Samsung is still striving to close the gap with its competitors. The company is working to improve the maturity of its 2nm process to meet the high-performance, low-power demands of advanced processes. Samsung’s the first-generation 3nm GAA process has achieved yield maturity and is set for mass production in the second half of the year.

In memory, Samsung is beginning to narrow the gap with SK Hynix in high-bandwidth memory (HBM). According to Bloomberg, Samsung has received certification for HBM3 chips from NVIDIA and expects to gain certification for the next-generation HBM3e within two to four months.

Jun emphasized that although Samsung is in a challenging situation, he is confident that with accumulated experience and technology, the company can quickly regain its competitive edge.

Read more

• [News] Samsung Sees Solid Demand for 3nm in 2H24, Aiming a Ninefold Increase in AI/HPC Sales by 2028
• [News] Samsung’s Q2 Profits Soar to USD 7.5 Billion, Seeing Strong Demand for HBM, DDR5 and Server SSD in 2H24

(Photo credit: Samsung)

According to a report by the Commercial Times, while TSMC, the global foundry leader, has established a plant in Kikuyo, Kumamoto City, Kyushu. ASE Technology Holdings (ASE), a giant in packaging industry, is setting up a plant in Kitakyushu as well. With these developments, Japan’s semiconductor production could potentially integrate both front-end and back-end processes, forming a cluster within Kyushu.

This development could lead to a revival of Kyushu’s semiconductor industry, once known as the “Silicon Island” in Japan, attracting more semiconductor supply chain companies to the region.

The report further notes that related equipment and inspection company, including MA-tek, semiconductor transmission and storage solutions provider Gudeng Precision, and semiconductor material distributor Topco Technologies Corp. (Topco) have all established bases in Kumamoto.

MA-tek, a leader in semiconductor inspection and analysis services, established its first Japanese laboratory in 2019 and a second one in Kumamoto in 2023. Since their establishment, these laboratories have consistently achieved growth rates higher than the company average.

With the rise of AI applications, many Japanese clients have AI chip development projects, leading to increased demand for MA-tek’s materials analysis (MA) and advanced process inspection services.

To capitalize on advanced process and packaging opportunities brought by AI, the company MAT has decided to increase its capital expenditure this year to between NTD 1.2 billion and NTD 1.4 billion.

These funds will be used to expand and upgrade the testing equipment and laboratory facilities in Nagoya and Kumamoto, and to establish a third laboratory in Hokkaido, which is expected to start contributing to revenue in Q1 2025.

On the other hand, Gudeng Precision is also planning to build a new plant in Kurume in Q2 this year, located between Fukuoka and Kumamoto, with a planned area of approximately 3,000 ping (about 10,000 square meters).

Gudeng Precision’s investment in Kurume, Japan, including equipment procurement, is estimated at about NTD 400 million to NTD 450 million. Construction is expected to begin by the end of this year, with production slated to start by the end of 2025.

Read more

• [News] TSMC’s JASM Kumamoto Plant 2 Greenlit, Construction Expected to Commence by Year’s End
• [News] Kumamoto Vying for TSMC’s Third Fab, Looking to Build Semiconductor Hub

(Photo credit: JASM)