According to a report from The Information, generative AI application giant OpenAI has held talks with several chip designers, including Broadcom, to discuss plans for developing new AI chip.

It’s reported that OpenAI is currently exploring the possibility of manufacturing its own AI chip. This move would not only allow for efficient integration of software and hardware,  but also help alleviate the current shortage of AI chips. Moreover, OpenAI is said to be actively recruiting former Google employees, hoping to leverage their experience and expertise in developing Tensor processors to create its own AI chip.

The report emphasized that there is little possibility for OpenAI to develop AI server chip that can rival that of NVIDIA, and it would take years of research and development to achieve any significant results.

However, OpenAI might be able to shorten the development time by actively drawing in former talents from Google and harnessing their expertise and experience in developing Tensor processors.

Previously, the industry pointed out that OpenAI CEO Sam Altman has formulated an ambitious AI chip development plan, aiming to raise USD 7 trillion to renovate the global semiconductor industry ecosystem and promote the development of the general AI industry.

Sam Altman also stated that this USD 7 trillion would bring about considerable investment in AI, enabling the fabrication of AI chip and the construction of AI-related infrastructures, which will ultimately translate into vast services to the world and substantial value to everyone.

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(Photo credit: Broadcom)

As the industry is entering the Angstrom era with semiconductor giants eagerly applying EUV machines to the advanced nodes, more details about Samsung’s 2nm have surfaced. According to the latest report by TheElec, Samsung’s 2nm process will feature 30% more extreme ultraviolet (EUV) layers than the 3nm node.

The report notes that Samsung’s 3nm node has 20 EUV mask layers, while the layers of the 2nm node will be increased to late-20. As the cost of manufacturing rises with the number of EUV mask layers, whether the wafer average selling price of Samsung’s 2nm will significantly increase attracts attention.

According to the report, the South Korean semiconductor giant first implemented EUV technology in its logic process nodes with 7nm in 2018. Since then, Samsung has increased the number of EUV layers or process steps with each subsequent node, moving from 5nm to 3nm. The report also states that Samsung’s 1.4nm process, set to begin production in 2027, is expected to feature over 30 EUV layers.

Meanwhile, Samsung is also using EUV in its DRAM production. For its Gen 6 10nm DRAM, Samsung has implemented up to 7 EUV layers, compared to 5 layers used by SK Hynix, TheElec states.

In comparison, according to an earlier report by AnandTech, TSMC’s standard N3 node includes up to 25 EUV layers. TSMC employs EUV double-patterning on some of these layers to achieve greater logic and SRAM transistor density compared to its N5 node.

It is also worth noting that as EUV layers increase with each node, foundries are vying to secure more EUV machines from ASML. The Dutch lithography equipment giant is said to ship over 70 EUV machines to TSMC in 2024 and 2025 in response to the strong demand of 2nm and 3nm, according to a report by MoneyDJ.

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• [News] Samsung Officially Secures Its First 2nm Order, Making AI Chips for Preferred Networks
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(Photo credit: ASML)

According to a report from global media outlet Financial Times citing sources, Chinese authorities plan to implement mandatory reviews of large AI models. Reportedly, Chinese government officials are testing the large language models of AI companies to ensure that the systems embody core socialist values.

The Cyberspace Administration of China is said to have required major tech companies such as ByteDance, Alibaba, Moonshot, and 01.AI, as well as AI startups, to participate in these mandatory reviews.

Sources indicate that this effort involves testing a range of responses from the large AI  models, including those on politically sensitive topics in China and related to Chinese President Xi Jinping. Officials from the Cyberspace Administration of China’s local branches are conducting the reviews, examining the models’ training data and other security processes.

A Hangzhou-based AI company reported that the Cyberspace Administration has dedicated teams for this task, who visit offices to conduct audits. The company mentioned that their first review did not pass, and after months of adjustments and communication with peers, they passed the second review.

Regarding the aforementioned matter, the Cyberspace Administration, ByteDance, Alibaba, Moonshot, Baidu, and 01.AI have not yet responded.

(Photo credit: Alibaba)

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According to a report from Economic Daily News, amid U.S. presidential candidate Donald Trump’s remarks claiming that Taiwan is taking away chip business and should pay the U.S. for defense, geopolitical risks have become another focal point at TSMC’s July 18 earnings call.

TSMC stated that whether the tariffs may increase is a hypothetical issue; if new tariff issues do arise, TSMC will discuss with customers and share the corresponding costs. However, it is still too early to discuss this in detail. Thus, TSMC Chairman C.C. Wei emphasized that TSMC’s overseas expansion strategy remains unchanged, including ongoing fab construction in Arizona, USA, and Kumamoto, Japan, with plans for future facilities in Europe as well.

Sources cited by the report indicate that TSMC’s statement of sharing corresponding costs with customers may imply that if additional tariffs are imposed, TSMC will seek customer assistance in bearing these costs, effectively raising prices.

TSMC pointed out that in a fragmented globalization environment, the costs for everyone—including TSMC, customers, competitors, and the entire semiconductor industry—will be higher.

TSMC plans to manage and minimize cost disparities through three methods: implementing strategic pricing to reflect the value of regional flexibility; closely cooperating with local administrations to ensure their support; and leveraging fundamental advantages such as leading manufacturing technologies and large-scale production capabilities that competitors cannot match.

Regarding TSMC’s progress on overseas expansion, the Arizona plant in the USA is scheduled to begin mass production of the 4nm process in the first half of 2025 as planned. The second plant in Arizona, following recent announcements, will offer both 3nm and 2nm processes and is expected to start mass production in 2028. The third plant in Arizona is expected to provide 2nm or more advanced process technologies.

Regarding the Kumamoto plant in Japan, the target is to commence mass production in the fourth quarter of this year. Previously, TSMC and its joint venture partners announced plans to establish a second wafer plant in Japan specializing in 40nm, 12/16nm, and 6/7nm process technologies. This plant aims to support strategic customers in consumer, automotive, industrial, and high-performance computing (HPC) applications. Construction of the second wafer plant in Japan is planned to start in the second half of 2024, with production expected to begin by the end of 2027.

As for its European plant, TSMC plans to begin construction on the Dresden, Germany, facility in the fourth quarter of 2024. TSMC emphasizes that its overseas expansion depends on customer demand and government support, aiming to maximize shareholder value and ensure that its long-term gross margin target remains above 53%.

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• [News] TSMC Pushes for FOPLP Mass Production by 2027, Reportedly Eyeing on Innolux’s Plant
• [News] TSMC Reports Strong Q2 Financial Results, with 3nm Accounting for 15% of Shipments

(Photo credit: TSMC)

To continue advancing Moore’s Law, TSMC Chairman and President C.C. Wei personally confirmed that FOPLP (Fan-Out Panel-Level Packaging) is in full swing. According to a report from Commercial Times, TSMC has established an R&D team and production line, currently still in the initial stages. Wei further forecasted that related achievements might be seen within three years.

Additionally, the sources cited by the same report also revealed that TSMC is interested in acquiring Innolux’s 5.5-generation LCD panel plant as well, partnering with Taiwanese companies to tackle new packaging processes. However, TSMC has not confirmed these rumors but emphasized that the company is continuously searching for suitable locations for expansion.

On average, die size continues to grow by 5-10%, reducing the number of chips that can be extracted from a single wafer and further squeezing wafer and advanced packaging capacity. Industry sources cited by Commercial Times believe that converting from wafer-level to panel-level packaging is more cost-effective.

Moreover, in response to Intel’s plan to mass-produce the industry’s first glass substrate technology for next-generation advanced packaging between 2026 and 2030, TSMC has started researching related glass substrate technologies to meet customer demands.

TSMC introduced the FOWLP technology named InFO (Integrated Fan-Out) in 2016, first used in the iPhone 7’s A10 processor. Subsequently, assembly and testing facilities actively promoted FOPLP solutions, looking to attract customers with lower production costs.

Currently, per the sources cited by Commercial Times, InFO has only one customer. Fan-Out packaging is a familiar area for TSMC, and future HPC (high-performance computing) clients like NVIDIA and AMD might adopt next-generation advanced packaging technology, replacing existing materials with glass substrates.

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(Photo credit: TSMC)