As top memory giants and AI chip companies all gear up for the combat of next-gen high bandwidth memory (HBM), JEDEC, the leader in the development of standards for the microelectronics industry, revealed the preliminary specifications of HBM4 last week. According to its press release and a report from Wccftech, HBM4 is poised to deliver substantial memory capacities, with densities up to 32Gb in 16-Hi stacks.

According to JEDEC, HBM4 aims to boost data processing rates while preserving key features such as higher bandwidth, reduced power consumption, and increased capacity per die or stack, which are crucial traits for applications that demand efficient management of large datasets and complex calculations, such as generative AI, high-performance computing, high-end graphics cards, and servers.

According to JEDEC’s preliminary specifications, HBM4 is anticipated to feature a “doubled channel count per stack” compared to HBM3, which indicates a higher utilization area, leading to significantly enhanced performance. It is also worth noting that in order to support device compatibility, the new standard ensures that a single controller can work with both HBM3 and HBM4.

JEDEC notes that HBM4 will specify 24 Gb and 32 Gb layers, offering support for TSV stacks ranging from 4-high to 16-high. The committee has initially agreed on speed bins up to 6.4 Gbps, with ongoing discussions for higher frequencies.

Interestingly enough, JEDEC did not specify how HBM4 integrates memory and logic semiconductors into a single package, which would be one of the major challenges the industry has been eagerly trying to solve.

Earlier in June, NVIDIA announced its next-gen Rubin GPU, targeting to be released in 2026, will feature 8 HBM4, while its Rubin Ultra GPU will come with 12 HBM4 chips.

The roadmaps for memory giants on HBM4 is generally in accordance with NVIDIA’s product pipeline. Samsung, for instance, is said to be developing a large-capacity HBM4 memory with a single stack capacity of 48GB, which is expected to enter production in 2025.

The current HBM market leader, SK hynix, on the other hand, has collaborated with TSMC on the development and production of HBM4, scheduled for mass production in 2026.

Micron has also disclosed its next-generation HBM memory, tentatively named HBM Next. It is expected that HBM Next will offer capacities of 36GB and 64GB, available in various configurations.

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• [News] The HBM4 Battle Begins! Memory Stacking Challenges Remain, Hybrid Bonding as the Key Breakthrough

(Photo credit: SK hynix)

To overcome the restrictions from the US and its allies, China is said to be heavily investing in semiconductor development. According to a report from Liberty Times Net, Huawei has completed its “Lianqiu Lake R&D Center” with a total investment exceeding CNY 10 billion (approximately USD 1.4 billion).

EE Times China further reported that Huawei’s “Lianqiu Lake R&D Center,” covering an area of 2,400 acres and a total construction area of 2.06 million square meters, has finally unveiled its mysterious veil after three years of construction.

This research center is designed with 40,000 offices and is expected to gradually attract about 35,000 Huawei R&D talents. It is divided into eight zones, with fully connected internal roads, a miniature train system, and elevated bridges. The park’s transportation includes a miniature train system with a total of eight stations. Once fully completed, Huawei plans to relocate its existing Shanghai R&D base in Jinqiao and other scattered office spaces to the ” Lianqiu Lake R&D Center.”

According to the reported plan, the R&D Center will consolidate Huawei’s research efforts in HiSilicon, wireless technology, flagship smartphone development, smart driving/automotive components, digital energy, and other areas. This move aims to provide advantageous support for Huawei’s expanding businesses such as 5G/6G, digital energy, and smart automotive solutions.

Regarding Huawei’s substantial investment in building this research center, tech media outlet “Tom’s Hardware” highlighted on July 14th that amid the US-China semiconductor rivalry and various US sanctions against Huawei, the company must bolster its research and development efforts. Consolidating multiple research centers allows Huawei to streamline operations and facilitate easier collaboration among different departments.

The report states that this flagship project showcases Huawei’s investment commitment in future technologies. The “Lianqiu Lake R&D Center” is larger in scale than the combined size of Apple Park and Microsoft’s Redmond Campus headquarters in Seattle.

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• [News] Huawei and XMC Collaborate to Develop HBM, Looking to Break Through U.S. Sanctions
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(Photo credit: Huawei)

According to the industry sources cited in a report from Economic Daily News, TSMC is gearing up to start production of NVIDIA’s latest Blackwell platform architecture graphics processors (GPU) on the 4nm process. In response to the strong customer demand, NVIDIA has reportedly increased its orders to TSMC by 25%.

This surge not only underscores the unprecedented boom in the AI market but also provides substantial momentum for TSMC’s performance in the second half of the year, setting the stage for an optimistic annual outlook adjustment, the report notes.

TSMC is set to hold an earnings conference call on July 18, in which it is expected to release the financial results of the second quarter as well as the guidance for the third quarter.

As TSMC will reportedly commence the production of NVIDIA’s Blackwell platform architecture GPU, which may be regarded as one of the most powerful AI chips, it is anticipated to be a focal point of discussion at TSMC’s upcoming earnings call.

Packed with 208 billion transistors, NVIDIA’s Blackwell-architecture GPUs are manufactured using a custom-built 4NP TSMC process with two-reticle limit GPU dies connected by 10 TB/second chip-to-chip link into a single, unified GPU.

The report further cited sources, revealing that international giants such as Amazon, Dell, Google, Meta, and Microsoft will adopt the NVIDIA Blackwell architecture GPU for AI servers. As demand exceeds expectations,NVIDIA is prompted to increase its orders with TSMC by approximately 25%.

As NVIDIA ramps up production of its Blackwell architecture GPUs, shipments of terminal server cabinets, including the GB200 NVL72 and GB200 NVL36 models, have seen a simultaneous significant increase. Initially expected to ship a combined total of 40,000 units, this figure has surged to 60,000 units, marking a 50% increase. Among them, the GB200 NVL36 accounts for the majority with 50,000 units.

The report estimates suggest that the average selling price of the GB200 NVL36 server cabinet is USD 1.8 million, while the GB200 NVL72 server cabinet commands an even higher price of USD 3 million. The GB200 NVL36 features 36 GB200 super chips, 18 Grace CPUs, and 36 enhanced B200 GPUs, whereas the GB200 NVL72 boasts 72 GB200 super chips, 36 Grace CPUs, and 72 B200 GPUs, which all contribute to TSMC’s momentum.

TSMC former Chairman Mark Liu, before handing over the reins in June, had already predicted that the demand for AI applications looks more optimistic compared to a year ago. Current Chairman C.C. Wei has also indicated that AI applications are just beginning, and he is optimistic like everyone else.

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• [News] End of an Era under Mark Liu’s Leadership, TSMC Discusses Future Development Plans
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(Photo credit: TSMC)

Global semiconductor giants are concentrating their R&D efforts on advanced packaging technologies to drive performance enhancements. According to a report from Commercial Times, as packaging technology progresses from 2.5D to 3D, chip stacking technologies have become a showcase for the competitive prowess of major companies.

“Hybrid Bonding” is seen as the key technology for future chip connections. In addition to international companies like Applied Materials and Besi actively positioning themselves, Taiwanese companies led by TSMC, including Gallant Micro, MPI Corporation, E&R Engineering Corporation, C SUN, Saultech, and Grand Process Technology, are also developing and seizing opportunities in Hybrid Bonding.

The report also cited industry sources, pointing out that Grand Process Technology has been supplying TSMC since the inception of InFO (Integrated Fan-Out Packaging). It is revealed that Grand Process Technology is also actively participating in future SoIC (System on Integrated Chips) advanced packaging, focusing on wafer cleaning and photoresist removal in etching processes.

It is indicated by the report that Grand Process Technology’s capacity will be operating at full speed until the first quarter of next year, with lead times extended to nine months. Last year’s orders are currently being installed gradually, with most concentrated on advanced packaging.

Semiconductor equipment manufacturer C SUN and its investment company Gallant Micro are currently investing in Hybrid Bonding-related equipment. C SUN primarily focuses on developing the best solutions for permanent bonding to enhance yield rates. Meanwhile, Gallant Micro leverages its relative advantage in chip sorting machines within its product line.

MPI Corporation, a testing interface vendor, has also entered the initial stages of inspection and analysis for Hybrid Bonding processes. Development of related products is nearing completion.

E&R Engineering Corporation also emphasizes that its top-tier plasma cleaning equipment is currently aimed at achieving high cleanliness of bonding surfaces to enhance adhesion.

Saultech Technology holds a positive outlook on the future market trends of Hybrid Bonding as well. The company has introduced equipment that corresponds to both Hybrid Bonding and Fan-Out technologies. Saultech has independently developed key technologies including bonding and die cleaning processes.

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• [News] Samsung and SK hynix to Implement Hybrid Bonding with 3D DRAM
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(Photo credit: Applied Materials)

Chul Joo Hwang, Chairman of South Korean semiconductor equipment company Jusung Engineering, recently stated that future semiconductors will stack transistors together, as the expansion of DRAM and logic chips has reached its limit. Stacking transistors like NAND is necessary to overcome these challenges.

According to a report from South Korean media outlet The Elec, Hwang believes this means developing more atomic layer deposition (ALD) technology to reduce the use of extreme ultraviolet (EUV) lithography steps in the production process of advanced chips.

ALD technology is a thin film process that allows materials to grow layer by layer, offering high uniformity, precise thickness control, and excellent step coverage, overcoming challenges faced by traditional process technologies.

Reportedly, stacking transistors can reduce the need for further scaling of transistors. As evidence, deep ultraviolet (DUV) equipment is expected to be used in 3D DRAM production.

Hwang believes that as stacking becomes increasingly important, the demand for ALD equipment will also rise. Additionally, the production of III-V semiconductors and IGZO semiconductors requires ALD equipment.

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• [News] Robust Demand in AI Drives South Korea’s Chip Exports in June to Record High
• [News] South Korea to Boost Semiconductor with a 26 Trillion Won Subsidy Program Starting in July

(Photo credit: Jusung Engineering)