In order to address the growing demand for high-performance memory solutions fueled by the expansion of the artificial intelligence (AI) market, Samsung Electronics has formed a new “HBM Development Team” within its Device Solutions (DS) Division to enhance its competitive edge in high-bandwidth memory (HBM), according to the latest report from Business Korea. The new team will concentrate on advancing the progress on HBM3, HBM3e, and the next-generation HBM4 technologies, the report noted.

This initiative comes shortly after the Korean memory giant changed its semiconductor business leader in May. Citing industry sources, the report stated that Samsung’s DS Division carried out an organizational restructuring centered on the establishment of the HBM Development Team.

Also, the move attracts attention as on July 4th, a report from Korea media outlet Newdaily indicated that Samsung has finally obtained approval from NVIDIA for qualification of its 5th generation HBM, HBM3e, though the company denied the market rumor afterwards.

Samsung has a long history of dedicating to HBM development. Since 2015, it has maintained an HBM development organization within its Memory Business Division. Earlier this year, the tech heavyweight also created a task force (TF) to boost its HBM competitiveness, and the new team will unify and enhance these ongoing efforts, the report noted.

According to the report, Samsung reached a significant milestone in February by developing the industry’s first HBM3e 12-layer stack, which offers the industry’s largest capacity of 36 gigabytes (GB). Samples of the HBM3e 8-layer and 12-layer stacks have already been sent to NVIDIA for quality testing.

Regarding the latest development, TrendForce reports that Samsung is still collaborating with NVIDIA and other major customers on the qualifications for both 8-hi and 12-hi HBM3e products. Samsung anticipates that its HBM3e qualification will be partially completed by the end of 3Q24.

According to TrendForce’s latest analysis on the HBM market, HBM production will be prioritized due to its profitability and increasing demand. However, limited yields of around 50–60% and a wafer area 60% larger than DRAM products mean a higher proportion of wafer input is required. Based on the TSV capacity of each company, HBM is expected to account for 35% of advanced process wafer input by the end of this year, with the remaining wafer capacity used for LPDDR5(X) and DDR5 products.

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• [News] Samsung’s HBM3e Reportedly Passed NVIDIA’s Certification Though It Denies the Rumor
• HBM3e Production Surge Expected to Make Up 35% of Advanced Process Wafer Input by End of 2024, Says TrendForce

(Photo credit: Samsung)

On July 1, GlobalFoundries (GF), a major foundry player, announced that it has acquired Tagore Technology’s production-verified proprietary GaN (Gallium nitride) power IP portfolio, which refers to a high-power density solution designed to enable higher efficiency and better performance of automobile, IoT, and AI data center applications where power supply is widely used.

Founded in January 2011, Tagore Technology focuses on developing GaN-on-Si (Gallium nitride on silicon) semiconductor technology for RF and power management applications.

As part of the acquisition, a team of veteran engineers from Tagore, dedicated to developing GaN technology, will join GF. “With this acquisition, GF takes another step toward accelerating the availability of GaN and empowering our customers to build the next generation of power management solutions that will reshape the future of mobility, connectivity and intelligence,” said Niels Anderskouv, chief business officer at GF.

It is worth mentioning that in February 2024, GF received a direct subsidy of USD 1.5 billion under the US CHIPS and Science Act, with part of the funds allocated to the mass production of critical technologies, including GaN.

By combining this manufacturing capability with the technical expertise of the Tagore team, GF is well positioned to transform the efficiency of AI systems and enable lower power consumption particularly pivotal for edge or IoT devices.

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• [News] SK keyfoundry Advances in GaN Power Semiconductors, Reportedly Producing for Tesla Soon
• [News] Infineon in GaN and SiC Expansion Drive Advancements in the New Energy Market

(Photo credit: GF)

According to a report from Reuters on July 4, consensus from 27 analysts compiled by LSEG SmartEstimate indicates that driven by the surge in demand for AI technology and the resulting rebound in memory prices, Samsung Electronics’ operating profit for Q2 2024 (ending June 30) is projected to skyrocket by 1,213% from KRW 670 billion in the same period last year to KRW 8.8 trillion (roughly USD 6.34 billion), marking the highest since Q3 2022.

Other memory giants are also optimistic about the operation afterwards. Take Micron as an example. Regarding the AI frenzy, Micron CEO Sanjay Mehrotra claimed that in the data center sector, rapidly growing AI demand enabled the company to grow its revenue by over 50% on a sequential basis.”

Mehrotra is also confident that Micron can deliver a substantial revenue record in fiscal 2025, with significantly improved profitability underpinned by our ongoing portfolio shift to higher-margin products.

On the other hand, SK Group also stated that by 2026, the group will invest KRW 80 trillion in AI and semiconductors, while continuing to streamline its businesses to increase profitability and return value to shareholders.

Read more

• [News] SK Hynix to Invest USD 75 Billion in AI Push, with 80% of It Flooding into HBM
• [News] Memory Giant Micron’s 3Q24 Earnings Report Released, Outlook Slightly Better Than Expected

(Photo credit: Samsung)

Google’s Tensor G4 could mark Samsung’s last mass-produced SoC, as earlier in May, Tensor G5 is reportedly adopting TSMC’s advanced 3nm process. Now here’s the latest development. According to a report by Wccftech, the chip, to be used in Google’s upcoming Pixel 10 lineup, has already reached tape-out, with mass production expected in 2025.

Google’s Tensor G5 would be its first fully self-designed smartphone SoC. Previous Tensor chips, somehow, were modifications from Samsung’s Exynos series, with Samsung being its foundry partner.

The report stated that Google’s decision to collaborate with TSMC is influenced by the Taiwanese semiconductor company’s established reliability in mass-producing wafers using its next-generation nodes.

Before Google, the foundry behemoth has already secured several major clients for its 3nm node. Both Qualcomm and Taiwanese smartphone fabless company MediaTek have reportedly adopted TSMC’s N3E node for their first 3nm chipsets. Apple’s upcoming A18 chips for iPhone 16 models, are said to be manufactured with TSMC’s N3E node as well, according to a report by Commercial Times.

On the other hand, regarding the progress of 3nm, Samsung is still struggling with the low yield rate for its latest Exynos 2500 processors. The company targets to increase the yield rate to over 60% before the product enters mass production, according to a previous report by Korean media outlet ZDNet Korea.

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• [News] Google Reportedly Shifts Orders from Samsung to TSMC for Its Upcoming Tensor G5 in the Pixel 10 Series

(Photo credit: Google)

According to a report from Notebookcheck citing market rumors, it’s suggested that the AMD Zen 6 architecture, codenamed Morpheus, will utilize 2nm and 3nm processes. The Zen 6 series includes three versions: Standard, Dense Classic, and Client Dense. Later rumors also indicate the architecture will feature three core configurations: 8-core (Zen 6), 16-core (Zen 6c), and 32-core (Zen 6c Extended).

The same report further indicates that, in the consumer market, the Zen 6 series will include high-end laptop versions like Medusa Point, platform versions for AM5 like Medusa Ridge, and versions suitable for both gaming laptops and desktops like Medusa Halo. AMD plans to launch the Zen 6 architecture in the second quarter of 2025, with production starting by the end of 2025, though mass production might be delayed to 2026.

AMD unveiled Strix Point at COMPUTEX 2024, featuring a combination of the Zen 5 series and RDNA 3.5 architecture. Strix Point’s launch was delayed by two quarters due to issues related to AMD’s plans for 3nm production, which were eventually canceled.

AMD also had plans for Strix Halo, rumored to use TSMC’s N3E process for producing IOD (input/output die) chips similar to Medusa Halo. Strix Halo’s launch was also delayed, possibly due to issues with the IOD chip.

Compared to the Zen 5 series architecture, the Zen 6 series is expected to feature a nearly redesigned memory controller and a new scheduling program. The Zen 6 architecture represents a significant overhaul similar to the Zen 2 architecture, with substantial changes. AMD is said to be looking to finalize the Zen 6 series design by the third quarter and commence production in 2025.

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• [News] A Quick Overview at TSMC’s Latest Collaboration with Intel, NVIDIA and AMD at COMPUTEX 2024
• [News] TSMC’s Advanced Packaging Capacity Fully Booked by NVIDIA and AMD Through Next Year

(Photo credit: AMD)