TSMC’s advanced CoWoS packaging capacity is in severe shortage, and just as the new plant in the Chiayi Park of Southern Taiwan Science Park began construction for expansion, according to a report from Economic Daily News citing sources, it has stated that TSMC intends to build another advanced packaging plant in Pingtung, which is located in southern Taiwan, and is currently in the site selection phase.

Regarding these rumors, TSMC has not yet responded. The relevant authorities, the Taiwanese National Science and Technology Council, stated that they have not heard of this and emphasized that any information about new plant constructions should be released by the company itself.

Currently, TSMC’s in-house packaging and testing capacities are located in Longtan, Hsinchu Science Park, Zhunan, Central Taiwan Science Park, and Southern Taiwan Science Park, with a new plant under construction in the Chiayi Park of Southern Taiwan Science Park. However, construction of one plant in the Chiayi Park was recently suspended due to the possible discovery of a historical site, prompting TSMC to initiate the construction of a second plant in the area.

If the advanced packaging plant in Pingtung is established, TSMC will have seven advanced packaging and testing sites in Taiwan, spanning across Taoyuan, Hsinchu, Miaoli, Taichung, Chiayi, Tainan, and Pingtung.

TSMC Chairman C.C.Wei previously mentioned that the demand for CoWoS capacity exceeds supply. Despite continuous expansion, TSMC still cannot meet all customer needs. Consequently, TSMC has increased outsourcing to professional packaging and testing subcontractors. TSMC is striving to expand its advanced CoWoS packaging capacity, with a target to more than double its in-house capacity this year and continue efforts next year to narrow the gap between supply and demand.

Industry sources cited in Commercial Time’s previous report have further indicated that by the end of next year, TSMC’s monthly CoWoS capacity will be increased to 60,000 wafers. With growing orders and a steep learning curve, the annual capacity is expected to surpass 600,000 wafers next year. As the semiconductor industry advances into the Angstrom Era, the gap in TSMC’s advanced packaging capacity will gradually widen.

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(Photo credit: TSMC)

Recently, it was reported that to meet the increasing demand for memory chips driven by the artificial intelligence (AI) boom, both Samsung Electronics and Micron set about ramping up their memory chip production capacity. Samsung plans to restart construction of the new Pyeongtaek plant (P5) infrastructure as early as 3Q24. Micron is building HBM testing and mass production lines at its headquarters in Boise, Idaho, U.S. and is considering producing HBM in Malaysia for the first time to meet the growing demand brought by the AI surge.

Samsung Restarts the Construction of P5 Plant

As per foreign media reports, Samsung has decided to restart the construction of the P5 infrastructure, which is expected to resume as early as 3Q24 and be completed in April 2027, though the actual date of starting production could be earlier.

Previously, P5 reportedly suspended construction at the end of January, which was said to be a temporary measure to coordinate progress, with investment not yet been finalized, as stated by Samsung at that time. Industry analysts interpret Samsung’s decision to resume P5 construction as a response to the AI-driven surge in demand for memory chip.

It is reported that the Samsung P5 plant is a large wafer fab with eight cleanrooms, while P1 to P4 only have four respectively, which makes Samsung’s plan to achieve large-scale production to meet market demand possible. However, no official announcement regarding the specific use of P5 has been disclosed so far.

According to Korean media reports, industry sources stated that Samsung held an internal management committee conference of the board of directors on May 30, during which they submitted and passed the agenda for the P5 infrastructure construction. The management committee was chaired by CEO and head of the DX division, Jong-hee Han, involving other members such as MX business head Noh Tae-moon, management support director Park Hak-gyu, and head of the memory business division Lee Jeong-bae.

Hwang Sang-joong, vice president and head of DRAM Product and Technology at Samsung, stated in March this year that HBM output for this year was expected to be 2.9 times that of last year. The company also announced its HBM roadmap, projecting that HBM shipment in 2026 would be 13.8 times the 2023 output, and by 2028, the annual HBM output would further increase to 23.1 times the 2023 level.

Micron Builds HBM Testing and Mass-Production Lines in the U.S.

On June 19, multiple media reported that Micron is building HBM testing and mass production lines at its headquarters in Boise, Idaho, and is considering producing HBM in Malaysia for the first time to meet the increased demand driven by the AI boom. Micron’s Boise wafer fab is reportedly to put into operation in 2025 and start DRAM production in 2026.

Previously, Micron announced plans to increase its HBM market share from the current “mid-single digits” to around 20% within a year. As of now, Micron has been expanding its memory capacity in various locations.

At the end of April, Micron officially announced that it had received USD 6.1 billion of government subsidies from the U.S. CHIPS and Science Act. These funds, along with additional state and local incentives, will support Micron in building a leading DRAM memory manufacturing plant in Idaho and two advanced DRAM memory manufacturing plants in Clay, New York.

The Idaho plant commenced construction in October 2023. Micron revealed that the plant is expected to run in 2025 and start DRAM production in 2026, with DRAM output increasing in line with industry demand. The New York project is in the phase of initial design, field study, and license application (NEPA application included). Construction of the wafer fab is expected to begin in 2025 and production in 2028, which will increase depending on market demand over the next decade. The press release noted that the U.S. government’s subsidies will support Micron’s plan to invest around USD 50 billion of total capital expenditures to lead domestic memory manufacturing by 2030.

In May, Japanese media Nikkan Kogyo Shimbun reported that Micron will pour JPY 600 to 800 billion to build an advanced DRAM chip plant using EUV lithography in Hiroshima, Japan. Construction is expected to start in early 2026 and be completed in late 2027 at the earliest. Japan had previously approved up to JPY 192 billion of subsidies to support Micron’s plant construction and next-generation chip production in Hiroshima.

The new Micron plant in Hiroshima will be located near the existing Fab 15, focusing on DRAM production, excluding back-end packaging and testing, with priority given to the fabrication of HBM products.

In October 2023, Micron inaugurated its second smart (Advanced assembly and test) plant in Penang, Malaysia, with an initial investment of USD 1 billion. Following the completion of the first plant, Micron allocated an additional USD 1 billion to expand the second smart plant, expanding its building area to 1.5 million square feet.

(Photo credit: Samsung)

TSMC is said to be entering the fan-out panel-level packaging (FO-PLP) sector, according to a previous report from Nikkei. Now, a report from Business Korea noted that Samsung is making significant strides in the PLP field, as the tech giant acquired the PLP business from Samsung Electro-Mechanics as early as in 2019.

It is interesting to note that TSMC has returned to the development of PLP now, while this technology is actually regarded by Samsung as the “secret weapon” to challenge TSMC’s InFO-WLP technology a few years ago.

In 2015, TSMC has secured all of Apple’s A10 orders by offering the InFO-WLP (Integrated Fan-Out Wafer Level Packaging) technology. According to a previous report by Korea media outlet ETNews, Samsung was prompted to take action, making the company to cooperate with Samsung Electro-Mechanics to start developing FO-PLP technology.

In 2019, Samsung acquired the PLP business from Samsung Electro-Mechanics for 785 billion won (approximately USD 581 million), a strategic move that has paved the way for its current advancements, according to Business Korea.

At the shareholders’ meeting in March this year, Kyung Kye-hyun, the former head of Samsung Electronics’ semiconductor (DS) division, highlighted the importance of PLP technology to the industry, Business Korea noted. Kyung stated that AI semiconductor dies, which are typically 600mm x 600mm or 800mm x 800mm in size, require technologies like PLP, while Samsung is actively developing this technology and collaborating with clients.

Samsung currently offers advanced packaging services such as I-Cube 2.5D packaging, X-Cube 3D IC packaging, and 2D FOPKG packaging. For applications requiring low-power memory integration, such as mobile phones or wearable devices, Samsung already provides platforms like fan-out panel-level packaging and fan-out wafer-level packaging.

On the other hand, TSMC is reportedly collaborating with equipment and material suppliers to develop the panel-level packaging technology, though the research is still in its early stages. By using a rectangular substrate for packaging, replacing the current traditional circular wafer, more chipsets can be accommodated on a single wafer.

The report by Nikkei mentioned that TSMC is currently experimenting with rectangular substrates measuring 515 mm in length and 510 mm in width, providing more than three times the usable area of a 12-inch wafer.

For now, TSMC’s CoWoS advanced chip packaging can combine two sets of NVIDIA Blackwell GPU chips and eight sets of high-bandwidth memory (HBM). As single chips need to accommodate more transistors and integrate more memory, the mainstream 12-inch wafer might not be sufficient for packaging advanced chips soon. The reason behind TSMC’s foray into PLP research, therefore, may be interpreted as a response to the booming AI demand.

Read more

• [News] TSMC Reportedly Develops Panel-Level Packaging, Another New Chip Packaging Tech
• [News] New Battleground for TSMC, Samsung & Intel in Panel-Level Packaging

(Photo credit: Samsung)

The U.S. Department of Commerce announced on June 24 the expansion of SelectTalentUSA, a joint initiative with the Departments of Labor and Education. The program, designed to provide technical assistance to foreign businesses in delivering recruitment and training programs for their U.S. workforce, will now include clients from Japan, South Korea, and Taiwan.

This move aims to better serve semiconductor and supply chain firms, along with other companies looking to establish or expand operations in the United States.

Launched in May 2023, SelectTalentUSA initially targeted Austria, Germany, Liechtenstein, and Switzerland, focusing on Registered Apprenticeships to foster cooperation and information exchange.

The initiative helps foreign investor companies form local and state partnerships, tailor their talent development strategies to the U.S. market, and leverage America’s diverse and skilled workforce.

The SelectUSA-led Interagency Investment Working Group (IIWG), comprising over 20 departments, supports SelectTalentUSA by increasing coordination and providing guidance on issues affecting business investment decisions. The IIWG connects foreign investors with resources and experts to establish quality training, education, and development programs.

During its pilot year, SelectUSA, along with the Departments of Labor and Education, conducted outreach to companies focusing on Registered Apprenticeships (RA). This effort has led to several companies signing, or nearing agreements to sign, RA standards with the Department of Labor to launch new U.S. training programs.

SelectTalentUSA promotes foreign direct investment that creates well-paying jobs in America, aligning with the Biden-Harris Administration’s goal of building an equitable economy and revitalizing overlooked communities. The program’s expansion allows more foreign investors to access the American workforce, build a skilled talent pipeline, and create quality job opportunities.

Additionally, it supports the goals of the CHIPS for America program, which aims to strengthen and revitalize the U.S. semiconductor research, development, and manufacturing sectors.

(Photo credit: TSMC)

Orders for thermal compression (TC) bonders from South Korean semiconductor equipment manufacturers are experiencing a surge, fueled by Samsung Electronics and SK Hynix ramping up their high-bandwidth memory (HBM) production. TC bonders play a pivotal role in HBM production by employing thermal compression to bond and stack chips on processed wafers, thereby significantly influencing HBM yield.

According to industry sources cited by The Chosun Daily, Samsung Electronics’ subsidiary SEMES has delivered nearly 100 TC bonders over the past year. Meanwhile, SK Hynix has inked a approximately $107.98 million contract with HANMI Semiconductor, which commands a 65% share of the TC bonder market.

Samsung Electronics and SK Hynix have developed distinct supply chains for thermal compression (TC) bonders. Samsung sources its equipment from Japan’s Toray and Sinkawa, as well as its subsidiary SEMES. In contrast, SK Hynix relies on Singapore’s ASMPT, HANMI Semiconductor, and Hanhwa Precision Machinery. Since last year, both companies have intensified localization efforts to decrease reliance on foreign equipment.

According to the Chosun Daily, HANMI Semiconductor, which co-developed TC bonders with SK Hynix in 2017, provides equipment for SK Hynix’s MR-MUF process, using an adhesive-like material for bonding DRAM chips. While HANMI’s TC bonders are compatible with both TC-NCF and MR-MUF processes, they are currently supplied only to SK Hynix and Micron.

On the other hand, SEMES, a specialist in TC bonders for the TC-NCF process used in high-bandwidth memory (HBM) stacking, supplies its equipment to Samsung. SEMES aims to exceed 250 billion won in TC bonder sales this year, up from around 100 billion won last year.

Regarding the HBM market, TrendForce notes that HBM3e may become the market mainstream for 2024, which is expected to account for 35% of advanced process wafer input by the end of 2024.

(Photo credit: SK hynix)