In early August, Taiwanese IC design giant MediaTek revealed its plan to unveil the Dimensity 9400 flagship series in October, designed to support most large language models on the market. Now more details regarding MediaTek’s ambition in AI have surfaced, as reports from Wccftech and Chinese media MyDrivers note that the company teams up with NVIDIA, targeting to launch their AI PC chip in the first half of 2025.

The reports indicate that the chip is currently in the design phase, with verification and sampling anticipated next quarter.

TrendForce projects that the Arm chip co-developed by MediaTek and NVIDIA, with adoption of Wi-Fi 7 and 5G, is slated to occupy a spot in the AI NB market since 2Q25, and initiate a new wave of technical innovation after 2025.

According to Wccftech, rumors about a custom chip from MediaTek for the AI PC market have been circulating for a while, and the excitement of the market skyrocketed when NVIDIA is reportedly joining the development.

The AI PC SoC is said to confront Qualcomm’s Snapdragon X Elite series. Wccftech suggests that the chip will be manufactured using TSMC’s 3nm node, based on ARM architecture.

With AI giant NVIDIA involved, the SoC is also likely to achieve breakthroughs in the integrated graphics arena, the report says. In addition, the report also notes that given MediaTek’s expertise in creating power-efficient mobile chips like the Dimensity 9400, the company may be well-equipped to develop a chip for the AI PC segment that delivers both strong performance and impressive efficiency.

MediaTek and NVIDIA are also collaborating on automotive chips, with plans to launch their first chip in early 2025. MediaTek CEO Rick Tsai mentioned earlier that though details are yet to be disclosed, significant advancements in the automotive sector are expected between 2027 and 2028.

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• [News] MediaTek Ventures into AI Accelerators, Aiming to Release Dimensity 9400 in October
• Penetration Rate of AI NBs to Arrive at 20% by 2025 as AI Applications Steadily Refine and Actuate Consumer Demand, Says TrendForce 

(Photo credit: MediaTek)

Facing increased market demand and the ongoing recovery of the memory industry, a report from Korean media outlet ETNews has reported that Samsung has confirmed its investment plan for the 6th-Generation DRAM production line at the Pyeongtaek P4 plant, with the goal of starting mass production in June 2025.

Reportedly, the 6th-generation DRAM, known as ‘1c ,’ is a next-generation DRAM utilizing 10nm-class technology. Despite it is said to be a product that has not yet been commercialized in the global semiconductor industry, both Samsung Electronics and SK hynix are already preparing for mass production.

Samsung’s Pyeongtaek P4 is a comprehensive semiconductor production center, divided into four phases.

As per ETNews, Samsung plans to initiate 1c DRAM production by the end of this year. The company is said to be considering launching HBM4 using 1c DRAM in the second half of 2025.

Given that HBM consumes significantly more DRAM than traditional memory, it is speculated by the report that Samsung’s construction of the 1c DRAM production line at the Pyeongtaek P4 plant may also be in preparation for HBM4.

As per TrendForce’s latest report on the memory industry, it’s revealed that DRAM and NAND Flash revenues are expected to see significant increases of 75% and 77%, respectively, in 2024, driven by increased bit demand, an improved supply-demand structure, and the rise of high-value products like HBM.

Furthermore, TrendForce also reports that Samsung’s P4L facility will be the key site for expanding memory capacity starting in 2025, starting with NAND production. Equipment installation for DRAM is expected to begin in mid-2025, with mass production of 1c nanometer DRAM slated to commence in 2026.

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• [News] Samsung Develops Custom HBM with Tech Giants, with Commercialization Expected in HBM4
• [News] Overview of Expansion Plans by HBM Giants

(Photo credit: Samsung)

Amid the advancement of emerging applications such as Artificial Intelligence (AI), High-Performance Computing (HPC), data center, and autonomous vehicle, fan-out panel-level packaging (FOPLP) technology has successfully garnered industry attention due to its advantages in significantly improving computing power, reducing latency, and increasing bandwidth. As a result, more manufacturers are entering this field.

Recently, semiconductor equipment manufacturer ACM Research Shanghai introduced the Ultra ECP ap-p panel-level electroplating equipment for FOPLP.

Prior to this, ACM has launched the Ultra C vac-p negative pressure cleaning equipment designed for fan-out panel-level packaging applications, signaling that ACM has successfully entered the high-growth FOPLP market.

It is worth mentioning that since the second quarter of this year, chip manufacturers like AMD have actively approached TSMC and professional OSAT (Outsourced Semiconductor Assembly and Test) companies to promote chip packaging using FOPLP technology, further increasing industry focus on FOPLP.

In fact, advanced packaging has an increasing demand for low-latency, high-bandwidth, and cost-effective semiconductor chips, and FOPLP offers high bandwidth and high-density chip interconnects, making it a technology with higher potential.

FOPLP is a process performed on larger square substrates, allowing multiple chips, passive components, and interconnects to be integrated into a single package on a panel, offering greater flexibility, scalability, and cost effectiveness.

By redistributing chips on larger rectangular panels, FOPLP largely reduces the costs of packaging large GPU and high-density, high-bandwidth memory (HBM).

It is reported that the utilization rate of traditional silicon wafers is less than 85%, while that of panels exceeds 95%. The effective area of a 600×600 mm panel is 5.7 times that of a 300 mm traditional silicon wafer, with overall panel cost expected to decrease by 66%.

The increase in area utilization leads to higher capacity, greater flexibility in AI chip design, and significant cost reduction.

Currently, major players in the FOPLP advanced packaging field include Powertech Technology, ASE Group, SPIL, TSMC, Innolux, JSnepes, and Samsung Electro-Mechanics.

TrendForce points out that FOPLP technology presents advantages and disadvantages, facing both opportunities and challenges. Its main strengths are lower unit cost and larger package size, but as its technology and equipment systems are still developing, the commercialization process is highly uncertain.

It is estimated that the mass production timeline for FOPLP in consumer IC and AI GPU may fall between the second half of 2024 to 2026, and 2027-2028, respectively.

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• [News] Innolux Targets to Begin FOPLP Mass Production by Year-End
• [News] TSMC Reportedly Forms a Team on FOPLP Development, with Mini Line on the Road 

(Photo credit: ACMR)

According to a report by Nikkei, Japanese chip manufacturer Rapidus plans to establish a fully automated production line using robots and AI in northern Japan to produce 2nm chips for advanced AI applications, with mass production anticipated as early as 2027.

Reportedly, Rapidus claims that automated production will significantly accelerate production times, reducing chip delivery time to just one-third of that of its competitors. The company’s fab is expected to complete its external structure by October, with EUV lithography system set to arrive in December.

Compared to other companies already operating fabs, building a fully automated plant could give Rapidus a significant advantage. While the front-end of chip manufacturing are already highly automated, the back-end processes, such as packaging and testing, remain labor-intensive.

Rapidus CEO Atsuyoshi Koike stated that this approach will deliver higher performance and faster turnaround times for the same 2nm products compared to other competing chipmakers.

Per a report from Tom’s Hardware, Rapidus is currently two years behind TSMC and Samsung, both of which are expected to begin 2nm chip production in 2025. If Rapidus can deliver chips faster without compromising on price or quality, it may secure a place in the market.

Despite the optimistic outlook, Rapidus faces operational challenges. The company revealed that it will need JPY 2 trillion (approximately USD 14 billion) to begin operation in 2025, and at least JPY 5 trillion in total for the start of mass production.

Although Rapidus has received JPY 920 billion in subsidies from the Japanese government, private companies remain hesitant to invest due to the company’s lack of track record.

Atsuyoshi Koike added that, given the current situation, it is difficult for Rapidus to secure private financing. The company is discussing ways to make financing easier, such as implementing a government loan guarantee system.

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• [News] Japanese Government Reportedly Plans to Offer Guaranteed Loans to Chip Startup Rapidus
• [News] Rapidus Partners RISC-V Player Esperanto, Targeting Low-Power AI Chip

(Photo credit: Rapidus)

According to a report from the South China Morning Post, the U.S. export controls, which are restricting China’s access to advanced chips and technology, have intensified China’s efforts to replace global semiconductor manufacturing equipment. However, industry sources have indicated that China still faces significant bottlenecks in this area.

The report mentions that Chinese semiconductor equipment companies like NAURA and AMEC are leading efforts to encourage local foundries to adopt domestic equipment.

Notably, sources cited in the same report also reveal that there is an unwritten rule among Chinese semiconductor fabs that locally-made tools should account for 70% of their production lines.

Per a report by TrendForce, Chinese manufacturers have achieved a self-sufficiency rate of 15% or higher in materials for mature processes, such as silicon wafers, photomasks, photoresists, electronic gases, and wet chemicals. However, items with a self-sufficiency rate still below 15% include photolithography equipment, photomasks, and EDA.

AMEC’s chairman and CEO, Gerald Yin Zhiyao, stated that China is expected to achieve a basic level of self-sufficiency in chip production equipment by this summer, something that was unimaginable just a few years ago.

He acknowledged that while there are still gaps in quality and reliability, China’s semiconductor supply chain can indeed achieve self-sufficiency. This, he suggested, is further evidence that U.S. export controls may have accelerated the development of China’s chip industry.

However, the report also pointed out that China remains constrained in one critical area: lithography technology, which is subject to the most stringent export controls.

Dutch company ASML is the sole supplier of Extreme Ultraviolet (EUV) systems, essential for producing advanced chips, and is also the main supplier of Deep Ultraviolet (DUV) systems needed for mature process chips.

President of foundry China Resources Microelectronics, Li Hong, stated that in 2023, only 1.2% of the lithography systems used by Chinese foundries was purchased from local suppliers.

In the second quarter of this year, ASML’s shipments to Chinese customers totaled EUR 2.35 billion, accounting for nearly half of its global sales. This indicates that China continues to rely heavily on ASML’s equipment in the legacy nodes, which is not subject to U.S. sanctions.

Paul Triolo, senior vice-president for China and technology policy lead at the U.S. consulting firm Albright Stonebridge Group, noted that the significant purchases of DUV lithography systems from ASML by Chinese companies highlight that SMEE, a major Chinese lithography equipment manufacturer, still lags behind ASML in reliably producing lithography systems for 28nm and below processes.

However, lithography technology is not the only bottleneck China faces. Li Hong also noted that the local supply ratios for ion implantation and inspection and metrology systems is only 1.4% and 2.4%, respectively.

As per Chinese customs data, the value of ion implantation systems imported by China in 2023 increased by 20% year-on-year to USD 1.3 billion.

A research report by Guohai Securities indicates as well that Chinese fabs rely heavily on metrology systems from companies like KLA, Applied Materials, and Japan’s Hitachi.

KLA reportedly holds a 50% global market share in inspection and metrology equipment.

An industry source cited in the report mentioned that the local supply ratio in the inspection and metrology sector is relatively low, with local substitution primarily occurring in lower-end products.

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• [News] China Lists Semiconductor Self-Reliance Challenges, Excluding Lithography Equipment
• [News] ASML Former CEO Predicts Chip War Between China and the US May Persist for Decades

(Photo credit: ASML)