On June 5th, NVIDIA CEO Jensen Huang gave a congratulatory gift to TSMC’s new chairman C.C. Wei, emphasizing that TSMC’s stock price has been undervalued. He supports Wei’s value theory and will back TSMC in its wafer and CoWoS pricing.

As per a report from Commercial Times citing sources, it’s estimated that both parties will negotiate chip prices for next year, potentially boosting TSMC’s revenue and profit margins further.

Jensen Huang revealed that he is not particularly worried about geopolitical issues because Taiwan has a strong supply chain. To ensure annual advancements in computing power, NVIDIA is building complete systems and creating more value.

Huang further emphasized that TSMC is not just manufacturing wafers but also handling numerous supply chain issues. He agrees that the current pricing is too low and will support TSMC’s price increase actions.

Notably, according to a previous Commercial Times’ report, NVIDIA’s H200 and B100 are said to adopt TSMC’s 4-nanometer and 3-nanometer processes, respectively.

Industry sources cited by Commercial Times also noted that in NVIDIA’s most recent quarterly report, its gross margin reached 78.36%, significantly outperforming AMD’s 46.78% and even TSMC’s first-quarter margin of 53.07%, exceeding it by 25 percentage points. If TSMC raises prices for its advanced processes, NVIDIA’s gross margin will remain unaffected. However, this price increase will dilute the gross margins for other companies using TSMC’s advanced processes, including Apple, AMD, and Qualcomm. 

In response to long-term capacity planning, TSMC held a board meeting on June 5th and approved a capital budget of USD 17.356 billion to expand advanced process capacity, primarily to address long-term capacity planning and the burgeoning demand for AI.

Semiconductors are fundamental to driving AI, with advanced processes and packaging being crucial competitive factors. Last year, TSMC’s advanced packaging capacity was strained, with ODM and OEM companies waiting for supply. Although there has been some relief in the first quarter of this year, the market demand is still unmet.

TSMC has confirmed the strong demand, stating that even tripling the capacity from 5nm to 3nm processes is insufficient, necessitating further capacity expansion. Sources cited by Commercial Times estimate that by the end of this year, TSMC’s CoWoS monthly capacity could reach 45,000 to 50,000 wafers, while SoIC capacity could reach 5,000 to 6,000 wafers.

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(Photo credit: TSMC)

If you happen to be a technology enthusiast, June would certainly be a month to watch. NVIDIA CEO Jensen Huang, joined by AMD CEO Lisa Su, visited Taiwan to announce their product roadmaps in COMPUTEX 2024. NVIDIA unveiled its new generation Rubin architecture, indicating that the R series products are expected to go into mass production in the fourth quarter of 2025.

On the other hand, AMD introduced its Ryzen AI 300 Series processors with the world’s most powerful Neural Processing Unit (NPU) for next-gen AI PCs, featuring a new Zen 5 CPU, as well as its latest AI chips, MI325X and MI350.

Interestingly enough, on 4 June, the world’s largest semiconductor foundry, TSMC, held its shareholders’ meeting in Hsinchu, Taiwan. When asked about the company’s relationships with NVIDIA and AMD, President C.C. Wei has reaffirmed TSMC’s strong relationships with the two tech giants, saying that the company will prosper with its clients.

What will be the highlights for TSMC’s progress in advanced logic process, and what are some of the most advanced products introduced in COMPUTEX made with TSMC’s advanced nodes? Please proceed to find out more. For now, TSMC’s 3nm seems to be the most popular node.

N3 Family

TSMC’s N3E (the more cost-effective second generation of the 3nm process) entered mass production in the fourth quarter of 2023. On the other hand, N3P (a more advanced version) is scheduled to enter mass production in the second half of 2024. Its yield performance is close to that of N3E, while customer product designs have already been tape-out.

TSMC states that due to N3P’s superior performance, better power consumption and area (PPA) characteristics, most 3nm products will eventually adopt the node. In the future, the industry may expect to see more high-end products manufactured with 3nm.

Regarding capacity, driven by the strong demand from HPC and mobile phone, TSMC has tripled its 3nm capacity in 2024 compared to that of 2023. However, as it is still not enough, the world’s largest semiconductor foundry has been striving to meet customer demand.

Intel’s Lunar Lake/ Arrow Lake

At COMPUTEX 2024, Intel CEO Pat Gelsinger introduced Lunar Lake, its latest AI PC chip, and thank its friend “TSMC” for their full support.

Starting Q3 2024 in time for the holiday season, Lunar Lake will power more than 80 new laptop designs across more than 20 original equipment manufacturers.

In a previous report by Wccftech, Gelsinger stated that Intel has collaborated with TSMC to power up its next-gen CPUs, adopting N3B, the first-generation 3nm process, for Lunar Lake and Arrow Lake.

NVIDIA’s Rubin

On the other hand, NVIDIA’s Rubin GPU architecture is now official: the Rubin GPU will feature 8 HBM4, while the Rubin Ultra GPU will come with 12 HBM4 chips, noted by Jensen Huang, CEO of NVIDIA.

Per a report from Wccftech, NVIDIA’s Rubin GPU is expected to utilize TSMC’s CoWoS-L packaging technology, along with its N3 process. Moreover, NVIDIA will use next-generation HBM4 DRAM to power its Rubin GPU.

Regarding NVIDIA’s previous GPUs, according to Commercial Times’ report, H200 and B100 reportedly are said to adopt TSMC’s 4-nanometer and 3-nanometer processes, respectively.

AMD’s MI 325X/ MI350

On 3 June, AMD CEO Lisa Su stated that the company’s relationship with TSMC is “very strong,” even as rumors have been circulating about a potential partnership with Samsung, TSMC’s main competitor.

AMD unveiled the company’s latest AI chip, MI325X, at the opening of COMPUTEX Taipei. Su emphasized that the MI325X boasts 30% faster computing speed compared to NVIDIA’s H200.

Furthermore, she also announced that AMD will release MI350 in 2025, which will be manufactured with TSMC’s 3nm process, while MI400 is expected to follow, launched in 2026.

When asked if AMD intended to procure chips manufactured using Samsung’s 3-nanometer (3nm) gate-all-around (GAA) process, Su reiterated AMD’s commitment to utilizing “the most advanced technology,” saying that AMD is certainly going to use 3 nm, 2 nm, and beyond. She also confirmed that there are several 3nm products currently being developed in collaboration with TSMC.

In addition to TSMC’s collaboration with clients on 3nm, this article also curates TSMC’s progresses on its 2nm node and other advanced processes. More information below:

N2 Family

The N2 process utilizes nanosheet transistors, thus would be able to offer superior energy efficiency. Currently, TSMC’s 2nm technology is progressing smoothly, with nanosheet conversion performance reaching the target of 90%, indicating that the yield exceeds 80%. Mass production is expected in 2025.

In the future, TSMC states that more members of the N2 family will emerge, including applications like N2P and N2X.

Read more

• [News] TSMC’s Advanced Packaging Capacity Fully Booked by NVIDIA and AMD Through Next Year
• [News] Samsung Reportedly Doing Its Utmost to Win 3nm GPU Orders from NVIDIA

(Photo credit: TSMC)

Qualcomm President & CEO Cristiano Amon, at COMPUTEX 2024, showcased devices powered by Snapdragon X Elite and Snapdragon X Plus processors, claiming them to be the only PCs capable of delivering Copilot+ PC experiences. Afterwards, during a media briefing, he disclosed Qualcomm’s plans on a dual-sourcing production strategy, indicating that the cooperation with Samsung has been considered, Korean media outlet Business Korea reported.

According to a previous report by Wccftech, Qualcomm’s Snapdragon 8 Gen 4, targeting to be launched in October, is rumored to utilize TSMC’s N3E node. However, the possibility of diversifying the production sources for Qualcomm’s “Snapdragon 8 Gen 5” smartphone chip has recently become a hot topic.

Regarding Qualcomm’s potential dual-sourcing policy, Amon emphasized that the primary focus should be on TSMC’s foundry production. However, he expressed willingness to collaborate with both TSMC and Samsung Electronics, according to Business Korea.

Initially, Samsung’s foundry was tasked with producing the first-generation Snapdragon 8 chip. However, it is rumored that overheating issues prompted Qualcomm to assign the following generations to be manufactured by TSMC.

Nonetheless, according to Business Korea, the recent launch of the Snapdragon X Elite, extensively integrated with Microsoft’s CoPilot+ PC, has sparked greater demand, which has prompted Qualcomm to reassess its collaboration with Samsung.

According to a previous report by Wccftech, it is likely that the Samsung’s 2nm technology will be utilized for the Snapdragon 8 Gen 5 in the Galaxy S26 series.

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• [News] Samsung Fails to Secure Qualcomm’s 3nm Orders for the Coming Year, Dual Foundry Strategy Postponed

(Photo credit: Qualcomm)

JEDEC (the Solid State Technology Association) recently confirmed that the long-used SO-DIMM and DIMM memory standards will be replaced by CAMM2 for DDR6 (LPDDR6 included).

According to a report from WeChat account DRAMeXchange, the minimum frequency for DDR6 memory is 8800MHz, which can be increased to 17.6GHz, with a theoretical maximum of up to 21GHz, far surpassing that of DDR4 and DDR5 memory. CAMM2 is a brand new memory standard that also supports DDR6 standard memory, making it suitable for large PC devices like desktop PC. JEDEC expects to complete the preliminary draft of the DDR6 memory standard within this year, with the official version 1.0 expected by 2Q25 at the earliest, and specific products likely coming in 4Q25 or in 2026.

LPDDR6 will adopt a new 24-bit wide channel design, with a maximum memory bandwidth of up to 38.4GB/s, significantly higher than the existing LPDDR5 standard. The maximum rate for LPDDR6 can reach 14.4Gbps and the minimum rate is 10.667Gbps, matching the highest rate of LPDDR5x and far exceeding LPDDR5’s 6.7Gbps.

It is learned that a true CAMM2-standard LPDDR6, with a 32GB specification for example, costs about USD 500, which is five times the price of LPDDR5 (SO-DIMM/DIMM) memory.

Considering market adoption, the industry believes that the new CAMM2 standard adopted by DDR6 requires large-scale replacement of existing production equipment, which will bring about a new cost structure. Meanwhile, the evolution of new standards in the existing market will face high cost issue, which will restrict the large-scale adoption of DDR6 or LPDDR6.

Currently, upstream manufacturers like Samsung, SK Hynix, and Micron already have some memory products supporting the CAMM2 standard. Among downstream brand manufacturers, Lenovo and Dell also follow up and Dell reportedly has used CAMM2 memory boards in its enterprise product line in 2023.

Read more

• [News] LPDDR6’s Bandwidth Expected to be Increased over 100%

(Photo credit: Samsung)

Vanguard International Semiconductor (VIS), an affiliate of TSMC, announced today a joint venture with NXP to build a 12-inch fab in Singapore. According to its press release, the construction is set to begin in the second half of 2024, with mass production expected by 2027. The initial investment for the fab is approximately USD 7.8 billion.

VIS stated in the official press release that it will establish a joint venture company, VisionPower Semiconductor Manufacturing Company (VSMC), with NXP in Singapore to build a 12-inch fab. The joint-venture fab will support 130nm to 40nm mixed-signal, power management and analog products, targeting the automotive, industrial, consumer and mobile end markets, of which its underlying process technologies are planned to be licensed and transferred to the joint venture from TSMC.

The company further stated that the joint venture will begin construction of the initial phase of the wafer fab in the second half of 2024, pending receipt of all required regulatory approvals, with initial production available to customers during 2027.

The joint venture will operate as an independent, commercial foundry supplier, providing assured proportional capacity to both equity partners, with an expected output of 55,000 300mm wafers per month in 2029. The joint venture will create approximately 1,500 jobs in Singapore. Upon the successful ramp of the initial phase, a second phase will be considered and developed pending commitments by both equity partners.

The total cost of the initial build out is anticipated to be USD 7.8 billion. VIS will inject USD 2.4 billion representing a 60 percent equity position in the joint venture and NXP will inject $1.6 billion for the remaining 40 percent equity position. VIS and NXP have agreed to contribute an additional USD 1.9 billion which will be utilized to support the long-term capacity infrastructure. The remaining funding including loans will be provided by third parties to the joint venture. The fab will be operated by VIS.

“VIS is pleased to work with leading global semiconductor company NXP to build our first 300mm fab. This project aligns with our long-term development strategies, demonstrating VIS’ commitment to meeting customer demands, and diversifying our manufacturing capabilities,” said VIS Chairman Leuh Fang.

“NXP continues to take proactive actions to ensure it has a manufacturing base which provides competitive cost, supply control, and geographic resilience to support our long-term growth objectives,” said Kurt Sievers, NXP President and CEO. “We believe VIS is well suited and fully understands the complexities involved in building and operating together with NXP a 300mm analog mixed signal fab. The joint venture partnership we intend to create with VIS perfectly aligns within NXP’s hybrid manufacturing strategy.”

Regarding this move, TrendForce posits that it reflects the trend of global supply chains shifting “Out of China, Out of Taiwan”(OOC/OOT), with Taiwanese companies accelerating their overseas expansion to improve regional capacity flexibility and competitiveness.

TrendForce noted that the semiconductor supply chain has been diversifying over the past two years to mitigate geopolitical and pandemic-related risks, forming two major segments: China’s domestic supply chain and a non-China supply chain. Recent US tariff increases have accelerated this shift, leading to increased orders from American customers.

Consequently, Vanguard’s capacity utilization rate is expected to rise to approximately 75% in the second half of this year, exceeding initial expectations. Additionally, inquiries for capacity at Vanguard’s existing Singapore Fab 3E plant have significantly increased, indicating potential support for the new plant’s capacity from customer demand and order transfers, according to Trendforce.

Read more

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(Photo credit: VIS)