Semiconductors


2024-08-02

[News] SK hynix Reportedly Develops NAND over 400 Layers, Eyeing Mass Production Ready by 2025

As the battle of HBM intensifies between memory giants, the competition of NAND is also heating up. According to a report by Korean media outlet etnews, SK hynix is developing 400-layer NAND flash memory, aiming to get the technology ready for mass production by the end of 2025.

Citing sources familiar with the matter, the report notes that SK hynix is currently working with supply chain partners to develop process technologies and equipment needed for 400-layer and above NANDs. As the company plans to apply hybrid bonding to achieve the breakthrough, many packaging materials and components suppliers are expected to enter the new supply chain.

According to the report, SK hynix is reviewing new materials for bonding and various technologies for connecting different wafers, including polishing, etching, deposition, and wiring. With the goal of getting the technology and infrastructure ready by the end of next year, full-scale production for the 400-layer NAND is anticipated to begin in the first half of 2026.

Currently, the Big Three in the memory sector are all trying to push the boundaries on the layers of NAND. Earlier in April, Samsung confirmed that it has begun mass production for its one-terabit (Tb) triple-level cell (TLC) 9th-generation vertical NAND (V-NAND), with the number of layers reaching 290. For now, the company aims to stack V-NAND to over 1000 layers by 2030.

Micron, on the other hand, has announced the 2650 client SSD, its first product built from 276-layer 3D NAND on July 30th. Japanese memory chipmaker Kioxia, after successfully increasing the number of 3D NAND layers to 218 in 2023, even stated that achieving a 1,000-layer level by 2027 would be possible.

In August, 2023, SK hynix showcased its sample of the world’s first 321-layer NAND product. Now, as the limit is expected to be pushed up to 400 layers, the company plans to apply hybrid bonding to the manufacturing, which adopts a “wafer-to-wafer” (W2W) structure, etnews notes.

According to the report, until now, SK hynix has been stacking cells on top of the peripherals, the driving circuit area, using the method of “Peripheral Under Cell (PUC)” to manufacture NAND. The structure is similar to a mixed-use high-rise apartment where the peripheral (commercial space) is at the bottom and the cells (residential units) are stacked on top.

However, as the number of NAND layers increases, the peripheral is prone to be damaged during the cell stacking process due to the high heat and pressure generated during the cell process, the report explains.

Therefore, SK hynix plans to apply hybrid bonding to overcome the issues. By implementing cells and peripherals on separate wafers and then bonding the two wafers together, the method allows the peripheral wafer that drive the cells to be separately manufactured, thus enabling a stable increase in NAND layers.

Regarding the progress on the development of 400-layer NAND, SK hynix stated that it cannot confirm details about its technology development or mass production timeline, the report notes.

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(Photo credit: SK hynix)

Please note that this article cites information from etnews.
2024-08-02

[News] IQE’s Taiwan Subsidiary Plans to Go Public on the Taiwan Stock Exchange

On July 31, IQE plc, the global supplier of compound semiconductor wafer products and advanced material solutions, announced the planned initial public offering (IPO) of the Group’s Taiwanese operating subsidiary (IQE Taiwan) on the Taiwan Stock Exchange (TWSE).

The Group intends to list IQE Taiwan on the TWSE and to sell a minority shareholding through a public offering, but it plans to retain control of IQE Taiwan and will continue to leverage its strategic value, with the proceeds of the public offering intended to be utilized across the Group to fund the growth strategy.

Currently, the IPO process is at an early stage, and IQE has engaged Taishin Securities Co. Ltd as its financial advisor to assist in preparing IQE Taiwan for the IPO. IQE explained that the IPO will be proceeded in two stages.

For the initial phase, IQE Taiwan is expected to be listed on the Emerging Market Board in 1H25, subject to usual regulatory procedures and requirements. Further transaction details and information regarding the process will be disclosed as appropriate.

As IQE is capitalizing on the market opportunities ahead, including in GaN Power, the company considers the listing of its Taiwan subsidiary as an exciting opportunity for the entire group, which will accelerate IQE’s investment in its strategy for growth.

Once the subsidiary is successfully listed, IQE is expected to maximize asset value and ensure supply reliability and flexibility for its global customers.

It’s worth noting that aside from IQE, GaN IDM Innoscience is promoting its IPO process on the Hong Kong Stock Exchange while TASC has spun off its subsidiary responsible for 8-inch GaN business and promoted its listing on TWSE, which all reflect the fact that GaN power semiconductor technologies are gaining traction, particularly with the development of AI server and low-altitude economy sectors.

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(Photo credit: IQE)

Please note that this article cites information from WeChat account DRAMeXchange.

2024-08-01

[News] Kioxia’s New NAND Flash Plant in Iwate Sets to Start Operation in Fall 2025

Japanese NAND flash giant Kioxia announced today (August 1st) that the building construction of Fab2 (K2) of its Kitakami Plant in Iwate Prefecture was completed in July. As demand is recovering, the company will gradually make capital investments while closely monitoring flash memory market trends. Kioxia plans to start operation at K2 in the fall of Calendar Year 2025, according to its press release.

A portion of investment for K2 will be subsidized by the Japanese government according to the plan approved in February 2024, according to Kioxia.

In addition, the company notes that some administration and engineering departments will move into a new administration building located adjacent to K2 beginning in November 2024 to oversee the operation of K2.

According to a report from Nikkei on July 31, Kioxia’s Kitakami Plant started production in 2020,with the construction of K2 began in 2022. Initially, K2 was scheduled to commence production in 2023.

However, due to a downturn in the memory market and weak demand for NAND Flash used in smartphones and PCs, Kioxia started to reduce production in October 2022, with the extent of production cuts exceeding 30%. As part of these production reduction measures, Kioxia postponed the production start of the K2 facility.

Nikkei’s report further indicates that with market conditions recovering, Kioxia ended its production cuts in June 2024, and the current production line utilization rate has returned to 100%.

To mass-produce advanced memory products, Kioxia, in collaboration with Western Digital (WD), plans to invest a total of 729 billion yen in the Yokkaichi and Kitakami plants, with the Japanese government providing up to 243 billion yen in subsidies.

The Kitakami plant will produce the most advanced “8th generation” memory, with a monthly production capacity of 25,000 wafers. These will be used in AI data centers, as well as in smartphones, PCs, and automotive applications.

On June 26, according to industry sources cited in a report from Reuters, Kioxia plans to submit an initial public offering (IPO) application to the Tokyo Stock Exchange in the near future, aiming to go public by the end of October. Sources indicate that Kioxia will submit its official IPO application by the end of August, with a target listing date at the end of October.

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(Photo credit: Kioxia)

Please note that this article cites information from NikkeiReuters and Kioxia.

2024-08-01

[News] MediaTek Ventures into AI Accelerators, Aiming to Release Dimensity 9400 in October

According to a report from Commercial Times, IC design giant MediaTek is making its move into the AI accelerator sector. MediaTek CEO Rick Tsai emphasized that MediaTek aims to be the best partner for edge AI, focusing on advanced technologies and 3nm process to optimize the power consumption and efficiency of its SoCs (system-on-chips).

Tsai mentioned that MediaTek will unveil its Dimensity 9400 flagship series of chips in October, designed to perfectly support most large language models on the market. He expressed confidence in achieving a more than 50% year-over-year revenue increase for flagship devices.

For the ASIC (Application-Specific Integrated Circuit) market, MediaTek has confirmed its entry into the AI accelerator field and will integrate CPUs as needed. ASICs are expected to start the revenue contribution  in the second half of next year.

Additionally, the TAM (Total Addressable Market) for generative AI is still in its early stages. MediaTek focuses on providing leading interconnect capabilities, such as SerDes IP and Ethernet PHY.

Regarding AI technology in the smartphone sector, Rick Tsai believes that flagship smartphones are seeing an increase in ASP, and there is a gradual shift towards high-end smartphones in the Chinese market. He noted that Chinese brands are actively developing AI, particularly in model development, such as open-source models like LLaMA 3.

At MediaTek’s earnings call on July 31st, Rick Tsai noted that the company anticipates a return to normal seasonal patterns in the second half of the year. The outlook for the fourth quarter will largely depend on consumer product demand.

Regarding the outlook in the third quarter, MediaTek expects the revenue to be flattish, ranging from NTD 123.5 billion to NTD 132.4 billion, compared with NTD 127.27 billion last quarter. Gross margin is projected to slide to 45.5-48.5%, from 48.8%, down 3.6 percentage points quarter over quarter and up 1.3 percentage points year-over-year.

Aside from the boost expected from the Dimensity 9400 flagship release, the company’s fourth-quarter market demand is projected to be relatively moderate, which is why the annual outlook remains unchanged. MediaTek expects its full-year gross margin to be between 46% and 48%.

Regarding TSMC’s pricing adjustments, Rick Tsai remains unperturbed, noting that all industry peers face similar cost pressures. MediaTek aims to reflect cost increases through pricing, with a gross margin target of 47% for new products. Progress has also been made in 3nm and 2nm processes, and MediaTek has secured its capacity needs for 2025 with TSMC.

Moreover, MediaTek and NVIDIA are collaborating on automotive chips, with plans to launch their first chip in early 2025. Rick Tsai mentioned that details are yet to be disclosed, but significant advancements in the automotive sector are expected between 2027 and 2028.

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(Photo credit: MediaTek)

Please note that this article cites information from Commercial Times.

2024-08-01

[News] Samsung’s 8-layer HBM3e to Start Mass Production in Q3, Driving HBM Sales to Soar 3-5 Times in 2H24

Samsung Electronics, which has been surround by concerns that its HBM3e products are still struggling to pass NVIDIA’s qualifications, has confirmed in its second quarter earnings call that the company’s fifth-generation 8-layer HBM3e is currently undergoing customer valuation, and is scheduled to enter mass production in the third quarter, according to a report by Business Korea.

TrendForce notes that Samsung’s recent progress on HBM3e qualification seems to be solid, and we can soon expect both 8hi and 12hi to be qualified in the near future. The company is eager to gain higher HBM market share from SK hynix so its 1alpha capacity has reserved for HBM3e. TrendForce believes that Samsung is going to be a very important supplier on HBM category.

Driven by the momentum, the report from Business Korea, citing an official speaking at the conference call on July 31st, states that the share of HBM3e chips within Samsung’s HBMs is anticipated to surpass the mid-10 percent range in the third quarter. Moreover, it is projected to speedily grow to 60% by the fourth quarter.

According to Samsung, its HBM sales in the second quarter already grew by around 50% from the previous quarter. Being ambitious about its HBM3 and HBM3e sales, Samsung projects its HBM sales will increase three to five times in the second half of 2024, driven by a steep rise of about two times each quarter.

Samsung has already taken a big leap on HBM as its HBM3 chips are said to have been cleared by NVIDIA last week. According to a previous report by Reuters, Samsung’s HBM3 will initially be used exclusively in the AI giant’s H20, which is tailored for the Chinese market.

On the other hand, the South Korean memory giant notes that it has completed the preparations for volume production of its 12-layer HBM3e chips. The company plans to expand the supply in the second half of 2024 to meet the schedules requested by multiple customers, according to Business Korea. The progress of its sixth-generation HBM4 is also on track, scheduled to begin shipping in the second half of 2025, Business Korea notes.

Samsung Electronics reported higher-than-expected financial results in the second quarter, with a six-fold year-on-year increase in net income, soaring from KRW 1.55 trillion won (USD 1.12 billion) to KRW 9.64 trillion (USD 6.96 billion), as demand for its advanced memory chips that are crucial for AI training remained strong.

SK hynix, as the current HBM market leader, has expressed its optimism in securing the throne as well. The company reportedly expects its HBM3e shipments to surpass those of HBM3 in the third quarter, with HBM3e accounting for more than half of the total HBM shipments in 2024. In addition, it expects to begin supplying 12-layer HBM3e products to customers in the fourth quarter.

Micron, on the other hand, has reportedly started mass production of 8-layer HBM3e as early as in February. The company reportedly plans to complete preparations for mass production of 12-layer HBM3e in the second half and supply it to major customers like NVIDIA in 2025.

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(Photo credit: Samsung)

Please note that this article cites information from Business Korea and Reuters.
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