TSMC continues to showcase its drive in the advanced packaging market. According to a report from MoneyDJ, TSMC has forecasted that CoWoS will remain in high demand through 2025, with potential for capacity to double in two consecutive years. TSMC is also entering the FOPLP (Fan-Out Panel-Level Packaging) space, a technology that OSATs and panel manufacturers have been developing for years, with a goal to launch it in three years.

TSMC’s stronghold on advanced packaging technologies has raised market concerns that OSATs may see their opportunities diminished as TSMC consolidates its market position.

During its earnings call, TSMC introduced “Foundry 2.0,” a new definition for the semiconductor manufacturing industry. This expanded definition now includes not only foundry services but also packaging, testing, photomask production, and other integrated component manufacturing, excluding memory production. TSMC further stated that this new definition will better reflect the company’s growing market opportunities and that the company will focus solely on cutting-edge back-end technologies.

Under this new definition, TSMC estimates the Foundry 2.0 industry will be nearly USD 250 billion in 2023, up from the previous estimate of USD 115 billion. With this new scope, the industry is expected to grow by 10% annually in 2024. Additionally, TSMC’s market share in Foundry 2.0 (logic semiconductor manufacturing) for 2023 is revised to 28%, with expectations for continued growth in 2024.

The sources cited by the report has pointed out that, observing TSMC’s process advancements, the 3nm process began mass production in 2022, with the 2nm process set for 2025, indicating a lengthening of the development cycle to three years.

Regarding the aforementioned nodes, advanced packaging may help enhance performance, reduce costs, and has the advantage of binding high-end products from top-tier clients. Additionally, the investment required for advanced packaging is significantly smaller compared to frontend technologies, making it a crucial area of focus.

The report continues to note that TSMC currently retains the majority of major CoWoS orders and collaborates with OSATs in the WoS segment. However, TSMC has reportedly yet finalized its CoW segment outsourcing orders.

Meanwhile, AMD and NVIDIA have reportedly turned to Amkor and ASE’s subsidiary, Siliconware, for CoWoS-related products, focusing on cost-sensitive high-performance products. Amkor is expected to supply about 70,000 to 80,000 units annually this year, while Siliconware can provide about 50,000 to 60,000 units.

Additionally, OSATs have been confined to mature IC FOPLP technologies for the past 7-8 years, whereas TSMC has announced it will launch its own FOPLP technology in three years.

TSMC’s planned FOPLP is a rectangular CoWoS-L concept, offering advantages in low unit cost and large-size packaging. However, it faces physical limitations such as issues in coating, spinning, and warping. TSMC, backed by a substantial equipment and materials supply chain, is well-positioned to address these challenges.

As for opportunities for other OSATs, the advanced packaging market is actually vast and can be broadly categorized into flip-chip, fan-out, fan-in, 2.5D/3D, and embedded die packaging.

These technologies can be integrated, and OSATs are not limited to TSMC’s top-tier Info, CoWoS, or SoIC technologies. OSATs can offer more cost-effective advanced packaging solutions compared to fabs, providing competitive alternatives in terms of cost and performance.

Read more

• [News] TSMC Pushes for FOPLP Mass Production by 2027, Reportedly Eyeing on Innolux’s Plant
• [News] TSMC Introduces “Foundry 2.0” to Include Packaging, Testing, Mask making and Others

(Photo credit: TSMC)

According to a report from The Information, generative AI application giant OpenAI has held talks with several chip designers, including Broadcom, to discuss plans for developing new AI chip.

It’s reported that OpenAI is currently exploring the possibility of manufacturing its own AI chip. This move would not only allow for efficient integration of software and hardware,  but also help alleviate the current shortage of AI chips. Moreover, OpenAI is said to be actively recruiting former Google employees, hoping to leverage their experience and expertise in developing Tensor processors to create its own AI chip.

The report emphasized that there is little possibility for OpenAI to develop AI server chip that can rival that of NVIDIA, and it would take years of research and development to achieve any significant results.

However, OpenAI might be able to shorten the development time by actively drawing in former talents from Google and harnessing their expertise and experience in developing Tensor processors.

Previously, the industry pointed out that OpenAI CEO Sam Altman has formulated an ambitious AI chip development plan, aiming to raise USD 7 trillion to renovate the global semiconductor industry ecosystem and promote the development of the general AI industry.

Sam Altman also stated that this USD 7 trillion would bring about considerable investment in AI, enabling the fabrication of AI chip and the construction of AI-related infrastructures, which will ultimately translate into vast services to the world and substantial value to everyone.

Read more

• [Insights] OpenAI CEO’s Ambition to Build Semiconductor Plant Grows Stronger
• [News] OpenAI Reportedly Expected to Gather with Samsung and SK Group for Deepened Chip Collaboration

(Photo credit: Broadcom)

As the industry is entering the Angstrom era with semiconductor giants eagerly applying EUV machines to the advanced nodes, more details about Samsung’s 2nm have surfaced. According to the latest report by TheElec, Samsung’s 2nm process will feature 30% more extreme ultraviolet (EUV) layers than the 3nm node.

The report notes that Samsung’s 3nm node has 20 EUV mask layers, while the layers of the 2nm node will be increased to late-20. As the cost of manufacturing rises with the number of EUV mask layers, whether the wafer average selling price of Samsung’s 2nm will significantly increase attracts attention.

According to the report, the South Korean semiconductor giant first implemented EUV technology in its logic process nodes with 7nm in 2018. Since then, Samsung has increased the number of EUV layers or process steps with each subsequent node, moving from 5nm to 3nm. The report also states that Samsung’s 1.4nm process, set to begin production in 2027, is expected to feature over 30 EUV layers.

Meanwhile, Samsung is also using EUV in its DRAM production. For its Gen 6 10nm DRAM, Samsung has implemented up to 7 EUV layers, compared to 5 layers used by SK Hynix, TheElec states.

In comparison, according to an earlier report by AnandTech, TSMC’s standard N3 node includes up to 25 EUV layers. TSMC employs EUV double-patterning on some of these layers to achieve greater logic and SRAM transistor density compared to its N5 node.

It is also worth noting that as EUV layers increase with each node, foundries are vying to secure more EUV machines from ASML. The Dutch lithography equipment giant is said to ship over 70 EUV machines to TSMC in 2024 and 2025 in response to the strong demand of 2nm and 3nm, according to a report by MoneyDJ.

Read more

• [News] Samsung Officially Secures Its First 2nm Order, Making AI Chips for Preferred Networks
• [News] Intel Secures First Batch of High-NA EUV Equipment from ASML, Ahead of Samsung and SK Hynix

(Photo credit: ASML)

According to a report from global media outlet Financial Times citing sources, Chinese authorities plan to implement mandatory reviews of large AI models. Reportedly, Chinese government officials are testing the large language models of AI companies to ensure that the systems embody core socialist values.

The Cyberspace Administration of China is said to have required major tech companies such as ByteDance, Alibaba, Moonshot, and 01.AI, as well as AI startups, to participate in these mandatory reviews.

Sources indicate that this effort involves testing a range of responses from the large AI  models, including those on politically sensitive topics in China and related to Chinese President Xi Jinping. Officials from the Cyberspace Administration of China’s local branches are conducting the reviews, examining the models’ training data and other security processes.

A Hangzhou-based AI company reported that the Cyberspace Administration has dedicated teams for this task, who visit offices to conduct audits. The company mentioned that their first review did not pass, and after months of adjustments and communication with peers, they passed the second review.

Regarding the aforementioned matter, the Cyberspace Administration, ByteDance, Alibaba, Moonshot, Baidu, and 01.AI have not yet responded.

(Photo credit: Alibaba)

Read more

• [News] China Plans to Set at Least 50 AI Standards by 2026, from Language Models to Semiconductors
• [News] China Targets Tech Leadership by 2035 in Six Areas, Including Semiconductors

According to a report from Economic Daily News, amid U.S. presidential candidate Donald Trump’s remarks claiming that Taiwan is taking away chip business and should pay the U.S. for defense, geopolitical risks have become another focal point at TSMC’s July 18 earnings call.

TSMC stated that whether the tariffs may increase is a hypothetical issue; if new tariff issues do arise, TSMC will discuss with customers and share the corresponding costs. However, it is still too early to discuss this in detail. Thus, TSMC Chairman C.C. Wei emphasized that TSMC’s overseas expansion strategy remains unchanged, including ongoing fab construction in Arizona, USA, and Kumamoto, Japan, with plans for future facilities in Europe as well.

Sources cited by the report indicate that TSMC’s statement of sharing corresponding costs with customers may imply that if additional tariffs are imposed, TSMC will seek customer assistance in bearing these costs, effectively raising prices.

TSMC pointed out that in a fragmented globalization environment, the costs for everyone—including TSMC, customers, competitors, and the entire semiconductor industry—will be higher.

TSMC plans to manage and minimize cost disparities through three methods: implementing strategic pricing to reflect the value of regional flexibility; closely cooperating with local administrations to ensure their support; and leveraging fundamental advantages such as leading manufacturing technologies and large-scale production capabilities that competitors cannot match.

Regarding TSMC’s progress on overseas expansion, the Arizona plant in the USA is scheduled to begin mass production of the 4nm process in the first half of 2025 as planned. The second plant in Arizona, following recent announcements, will offer both 3nm and 2nm processes and is expected to start mass production in 2028. The third plant in Arizona is expected to provide 2nm or more advanced process technologies.

Regarding the Kumamoto plant in Japan, the target is to commence mass production in the fourth quarter of this year. Previously, TSMC and its joint venture partners announced plans to establish a second wafer plant in Japan specializing in 40nm, 12/16nm, and 6/7nm process technologies. This plant aims to support strategic customers in consumer, automotive, industrial, and high-performance computing (HPC) applications. Construction of the second wafer plant in Japan is planned to start in the second half of 2024, with production expected to begin by the end of 2027.

As for its European plant, TSMC plans to begin construction on the Dresden, Germany, facility in the fourth quarter of 2024. TSMC emphasizes that its overseas expansion depends on customer demand and government support, aiming to maximize shareholder value and ensure that its long-term gross margin target remains above 53%.

Read more

• [News] TSMC Pushes for FOPLP Mass Production by 2027, Reportedly Eyeing on Innolux’s Plant
• [News] TSMC Reports Strong Q2 Financial Results, with 3nm Accounting for 15% of Shipments

(Photo credit: TSMC)