On June 18th, Belgium’s microelectronics research center IMEC showcased the first CMOS CFET device featuring stacked bottom and top source/drain contacts at the 2024 IEEE VLSI Technology and Circuits Symposium (2024 VLSI). Although the results were achieved using front-side lithography techniques for both contacts, imec also demonstrated the feasibility of transferring the bottom contacts to the back side of the wafer, which potentially increases the survival rate of top devices from 11% to 79%.

IMEC explained that their logic technology roadmap envisions the introduction of Complementary Field-Effect Transistor (CFET) technology into device architectures at the A7 node. Paired with advanced wiring technologies, CFET is expected to reduce the standard cell height from 5T to 4T or even lower without sacrificing performance. Among the different approaches to integrating vertically stacked nMOS and pMOS structures, monolithic integration is considered the least disruptive compared to existing nanosheet process flows.

At VLSI Symposium 2024, IMEC demonstrated for the first time a functional monolithic CMOS CFET device with both top and bottom contacts. The device features a gate length of 18nm, a gate pitch of 60nm, and a vertical distance of 50nm between the n-type and p-type. The process flow IMEC’s proposed includes two CFET-specific modules: Middle Dielectric Isolation (MDI) and stacked bottom and top contacts.

MDI is a module pioneered by IMEC to isolate the top and bottom gates and to differentiate threshold voltage settings between n-type and p-type devices. Based on modifications to the “active” multilayer Si/SiGe stack in CFET, MDI module allows for the co-integration of internal spacers—a feature unique to nanosheets that isolates the gate from the source/drain.

“We obtained the best results in terms of process control with an MDI-first approach, i.e., before source/drain recess – the step where nanosheets and MDI are ‘cleaved’ to gain access to the channel sidewalls and start source/drain epi. An innovative source/drain recess etch with ‘in-situ capping’ enables MDI-first by protecting the gate hardmask/gate spacer during the source/drain recess.” stated Naoto Horiguchi, IMEC’s CMOS device technology director, as per a report from IMEC.

The second critical module is the formation of stacked source/drain bottom and top contacts, vertically separated by dielectric isolation. Key steps involve bottom contact metal filling and etching, followed by dielectric filling and etching—all completed within the confined space of the MDI stack.

Naoto Horiguchi noted that developing bottom contacts from the front side encountered many challenges, which potentially impacts bottom contact resistance and limits the process window for top devices. At VLSI 2024, IMEC indicated that despite additional processes like wafer bonding and thinning, this design is proved feasible, making the backside bottom contact structure an attractive option for the industry. Currently, research is underway to determine the optimal contact wiring method.

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• [News] TSMC’s Latest Advancements in CFET, 3D Stacking, and Silicon Photonics

(Photo credit: IMEC)

SK keyfoundry, a subsidiary of memory giant SK hynix, has achieved notable progress in the development of Gallium Nitride (GaN) power semiconductors. According to the latest report by Business Korea, the foundry would begin producing power semiconductors for Tesla in the second half of 2024.

According to the report, SK keyfoundry announced in early June that it has achieved the primary device characteristics of a 650V GaN High Electron Mobility Transistor (HEMT), which surpasses traditional silicon-based semiconductors in both efficiency and durability. This advancement aligns with SK keyfoundry’s plan to finalize the development of GaN power semiconductors by the end of this year.

It is worth noting that TSMC has also entered the GaN market a few years ago, as it provides GaN process for manufacturing 100/650V discrete GaN power devices for customers. For instance, in 2020, the world’s largest foundry has announced to collaborate with STMicroelectronics. According to its press release, ST’s GaN products will be manufactured using TSMC’s leading GaN process technology, including applications relating to automotive converters and chargers for hybrid and electric vehicles.

Regarding the development of SK keyfoundry, Business Korea noted that the company established an official team in 2022 to focus on the development of GaN technologies. Citing industry sources on June 20^th, the report stated that SK keyfoundry will reportedly begin producing power semiconductors for Tesla in the second half of this year.

Moreover, it also mulls to broaden its business scope, entering markets like fast-charging adapters, data centers, and energy storage systems afterwards. Starting in November, the company plans to manufacture power management chips (PMIC) at its 8-inch wafer fab in Cheongju.

Though foundries have not significantly contributed to SK hynix’s revenue so far, the development of power semiconductors could boost overall foundry sales. According to the report, SK keyfoundry also provides contract manufacturing for non-memory semiconductors such as Display Driver ICs (DDI) and Microcontroller Units (MCU), further diversifying its product lineup.

In the current landscape of the new energy market, third-generation semiconductors such as SiC and GaN have gained significant traction. SiC (Silicon Carbide) and GaN could offer significant benefits over traditional silicon.

To elaborate, semiconductor materials have the so-called “bandgap,” an energy range in a solid where no electrons can exist. According to German chipmaker Infineon, GaN has a bandgap of 3.4 eV, compared to silicon’s 1.12 eV bandgap. The wider bandgap of GaN allows it to sustain higher voltages and temperatures than silicon. While SiC dominates the high-power domain, GaN excels at lower power levels, offering lower conduction losses.

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• [News] Infineon in GaN and SiC Expansion Drive Advancements in the New Energy Market

(Photo credit: SK keyfoundry)

According to a report from CNA, Taiwanese semiconductor testing and packaging giant ASE announced on June 21st that it will collaborate with Hung Ching Development & Construction Corporation to jointly build the K28 plant in Kaohsiung. Scheduled for completion in Q4 2026, the facility will reportedly focus on advanced packaging and final testing in order to meet the high-performance computing and cooling demands of AI chips.

ASE’s CFO Joseph Tung stated that ASE Semiconductor is planning for operational growth at its Kaohsiung facilities. To meet the demand for advanced packaging processes, high-performance computing for AI chips and cooling, the company is developing land in Dashe, Kaohsiung in two phases. The first phase, K27 plant, was completed and moved-in in 2023, while the K28 plant, the second phase, aims to be completed by Q4 2026.

As reported by CNA citing sources, ASE Kaohsiung Plant contributes approximately 20% to ASE Technology Holding Co., Ltd.’s total revenue. The plant specializes in providing services such as packaging, wafer bumping, probe testing, materials, and final testing. It has also developed several smart factories focusing on advanced processes, including Fan-out packaging, System-in-Package (SiP), wafer bumping, and Flip Chip packaging.

These technologies are primarily used in automotive, medical, IoT, high-speed computing, artificial intelligence, and application processor fields.

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• [News] Following TSMC, ASE Reportedly Plans to Establish Plant in Kumamoto
• [News] ASE Expands Production at Kaohsiung Plant, Focusing on Advanced Packaging for AI Chips

According to a previous report from Nikkei citing sources, TSMC is rumored to be entering the fan-out panel-level packaging sector. As cited in a report from UDN, Intel and Samsung have also announced plans to invest in this area. With TSMC, the leading wafer foundry, joining the fray, the three semiconductor giants are set to compete in fan-out panel-level packaging.

TSMC stated yesterday that the company is closely monitoring the progress and development of advanced packaging technologies, including panel-level packaging technology.

Nikkei reported that in response to future AI demand trends, TSMC is collaborating with equipment and material suppliers to develop new advanced chip packaging technology. This technology uses a rectangular substrate for packaging, replacing the current traditional circular wafer, to accommodate more chipsets on a single wafer. The report further mentioned that TSMC’s research is still in its early stages and might take several years to commercialize, but it represents a significant technological shift.

Reportedly, TSMC previously considered the challenge of using rectangular substrates to be too high, requiring substantial time and effort from both the company and its suppliers, along with upgrades or replacements of many production tools and materials.

Nikkei  also mentioned that TSMC is currently experimenting with rectangular substrates measuring 515 mm in length and 510 mm in width, providing more than three times the usable area of a 12-inch wafer.

TSMC is expanding its advanced chip packaging capacity, with the expansion of the Taichung plant mainly for NVIDIA, while the Tainan plant is primarily for Amazon and its chip design partner Alchip Technologies.

TSMC’s CoWoS advanced chip packaging can combine two sets of NVIDIA Blackwell GPU chips and eight sets of high-bandwidth memory (HBM). As single chips need to accommodate more transistors and integrate more memory, the mainstream 12-inch wafer might not be sufficient for packaging advanced chips in two years.

Samsung and Intel have also recognized the aforementioned issues and are investing in next-generation advanced packaging technologies.

Samsung currently offers advanced packaging services such as I-Cube 2.5D packaging, X-Cube 3D IC packaging, and 2D FOPKG packaging. For applications requiring low-power memory integration, such as mobile phones or wearable devices, Samsung already provides platforms like fan-out panel-level packaging and fan-out wafer-level packaging.

Intel is planning to launch the industry’s first glass substrate solution for next-generation advanced packaging, with mass production scheduled between 2026 and 2030. Intel anticipates that data centers, AI, and graphics processing—markets that require larger volume packaging and higher-speed applications and workloads—will be the first to adopt this technology.

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• [News] TSMC Reportedly Develops Panel-Level Packaging, Another New Chip Packaging Tech
• [News] Samsung Reportedly Targets Q4 Trial Production of SiP Glass Substrate, Competing with Intel in the Advanced Packaging Market

(Photo credit: Intel)

As China keeps reducing its reliance on the global semiconductor supply chain with strong support from the authority, two major smartphone manufacturers reportedly claim to have already taped out their own 4nm mobile processors. According to the reports by Liberty Times and Commercial Times, Xiaomi and Unisoc, by using foreign IP cores from ARM and IMG, have successfully taped out domestic 4nm chips.

According to the latest data from TrendForce, Xiaomi (including Xiaomi, Redmi, and Poco) has moved past last year’s high inventory issues, achieving a total production of 41.1 million units in the first quarter and ranking third globally in market share, only after Samsung and Apple. Oppo, Transsion and Vivo are the other three Chinese smartphone brands having made it to the top six regarding global shipments.

Shanghai-based fabless chip firm Unisoc, on the other hand, is specialized in areas including 2G/3G/4G/5G, Wi-Fi, Bluetooth, TV FM, satellite communications and other related technologies, according to its website.

Citing comments from Chinese tech blogger “Oneline Technology,” the reports point out that Xiaomi’s self-developed chip has made a significant leap forward, while the performance of its 4nm chip is similar to that of Huawei’s Kirin 9000s, and is expected to be seen this year. Huawei’s Kirin 9000s is reportedly manufactured by SMIC’s 7nm.

Citing another Chinese blogger, “Fixed Focus Digital,” the reports mention that Unisoc’s 4nm chip has already taped out, achieving performance levels comparable to Qualcomm’s Snapdragon 888.

Regarding the timeline for Chinese domestically produced smartphone SoCs to reach 4nm, the reports, citing industry insiders, state that it is more likely to happen in 2026. For now, MediaTek and Qualcomm still dominate Chinese’s smartphone chip market.

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• Q1 Smartphone Production Increases Due to Low Base Last Year, Expected to Decline 5–10% in Q2, Says TrendForce

(Photo credit: Unisoc)