According to a report from global media Reuters, the Indian software company Zoho plans to invest USD 700 million in the chip manufacturing sector.

Founded in 1996 and currently headquartered in Tamil Nadu, India, Zoho provides software and related services to businesses across 150 countries.

Zoho is considering the production of compound semiconductors and is seeking incentives from the Indian government. The proposal is currently being reviewed by the committee responsible for promoting India’s chip initiative under the Ministry of Electronics and Information Technology.

Compound semiconductors are semiconductor materials composed of two or more different elements. Compared to traditional silicon (Si) semiconductors, compound semiconductors generally boast higher electron mobility, wider bandgap, and better thermal stability and radiation resistance. These properties make them suitable for applications that require high speed, high frequency, high temperature, and high efficiency. Compound semiconductor materials abound, among which silicon carbide (SiC) and gallium nitride (GaN) are representatives. Currently, both materials are sought-after in consumer electronics and EV markets.

In recent years, India has actively promoted chip assembly and local production as a way of becoming a key player in global semiconductor market. The industry source points out that India’s chip initiative aims to strengthen the country’s position and competitiveness in global semiconductor industry through increased investment, international cooperation, infrastructure development, and talent cultivation.

In February 2024, India approved a semiconductor manufacturing investment plan totaling INR 1.26 trillion (USD 15.2 billion), covering wafer fabrication and chip packaging sectors, inclusive of India’s first fab, a collaboration between Tata Group and Powerchip.

The plant is expected to produce 50,000 wafers per month, covering multiple mature nodes including 28nm, 40nm, 55nm, 90nm, and 110nm. The goal is to produce 3 billion chips annually for various segments, such as high-power computing, EV, telecommunication, and power electronic.

Read more

• [News] 12-Inch Wafer Capacity Construction Going Full Steam
• [News] PSMC Collaborates with Tata to Establish India’s First Fab

(Photo credit: iStock)

Intel’s early adoption of ASML’s High Numerical Aperture Extreme Ultraviolet Lithography (High-NA EUV) equipment is seen by many as a crucial move for Intel to reclaim its technological leadership. Yet, according to a report from CNA, industry sources cited in the report have warned that the high cost of High-NA EUV could lead Intel to face the dilemma of expanding losses.

As Intel secures High-NA EUV equipment, the Korean media outlet TheElec reported that ASML plans to manufacture five High-NA EUV equipment this year, all of which have been booked by Intel. TSMC’s decision to continue using existing EUV equipment for its A16 process, rather than adopting High-NA EUV, has drawn significant attention and sparked lively discussion.

Per a report from Reuters, Intel CEO Pat Gelsinger has acknowledged that the previous decision to oppose using ASML’s EUV equipment was a mistake, which hampered the profitability of Intel’s foundry business. He stated that, with the adoption of EUV equipment, Intel is now highly competitive in terms of price and performance. There is widespread interest in whether Intel’s early adoption of High-NA EUV equipment will help it regain its position as a technology leader.

On the other hand, TSMC plans to mass-produce its A16 technology by 2026, combining nanosheet transistors with a supertrack architecture, garnering attention from the industry.

Ray Yang, the consulting director at Industry, Science and Technology International Strategy Center of ITRI (Industrial Technology Research Institute), stated that TSMC’s decision not to adopt High-NA EUV equipment for the A16 process was likely made after a comprehensive evaluation.

Yang mentioned that TSMC is undoubtedly aware of the benefits that High-NA EUV equipment can bring. However, given the high costs, TSMC has chosen to meet its customers’ diverse needs through other means.

According to ASML, High-NA EUV equipment increases the numerical aperture from 0.33 to 0.55, providing higher-resolution imaging capabilities. This improvement enhances precision and clarity, simplifies the manufacturing process, reduces production time, and boosts production efficiency.

During a technical symposium in Amsterdam on May 14th, TSMC’s Senior Vice President of Business Development and Co-Chief Operating Officer, Dr. Kevin Zhang, remarked that ‘I like the high-NA EUV’s capability, but I don’t like the sticker price.’

Each EUV system from ASML costs around USD 180 million, while High-NA EUV equipment is priced at USD 380 million, more than double the cost of EUV.

Ray Yang noted that the importance of advanced semiconductor packaging is increasing and will play a crucial supporting role. He argued that Intel’s rush to acquire High-NA EUV equipment is a case of choosing the wrong battlefield and weapon because High-NA EUV equipment is not the sole decisive factor for future success.

Ray Yang stated that as the global leader in semiconductor foundry services, TSMC has numerous customers, a comprehensive ecosystem, and ample capital. If customers demand and are willing to pay higher prices, TSMC will undoubtedly adopt High-NA EUV equipment.

Yang noted that TSMC is taking a cautious approach to adopting High-NA EUV equipment, likely after thoroughly considering its necessity. If Intel makes significant purchases of High-NA EUV equipment, its future capacity utilization will be worth observing, as it might face the risk of increased losses.

Currently, both TSMC and Samsung utilize EUV equipment for manufacturing, covering TSMC’s 7nm, 5nm, and 3nm processes and Samsung’s EUV Line (7nm, 5nm, and 4nm) located in Hwaseong, Korea, along with the 3nm GAA process.

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• [News] How Costly is the High-NA EUV? TSMC Reportedly Shocked, Considering Not Using the Equipment in its A16 Node
• [News] Intel Secures First Batch of High-NA EUV Equipment from ASML, Ahead of Samsung and SK Hynix

(Photo credit: ASML)

The recovery in demand for PCs and smartphones will take time, leading to a halt in the upward trend of DRAM prices, remaining stable for two consecutive months. However, the rapid growth in demand for High Bandwidth Memory (HBM), essential for data center servers and generative AI, is expected to boost future DRAM prices as the production trend of HBM rises.

The Nikkei News reported on May 18th that the recovery in demand for PCs and smartphones will take time, leading to a halt in the upward trend of DRAM prices used in smartphones, PCs, and data center servers for temporary data storage.

In April 2024, the wholesale price (bulk transaction price) of the benchmark product DDR4 8Gb was around USD 1.95 per unit, and the price of the smaller capacity 4Gb product was around USD 1.50 per unit, both remaining unchanged from the previous month (March 2024) and marking the second consecutive month of stability.

As of February 2024, DRAM prices had risen for four consecutive months. DRAM wholesale prices are negotiated between memory manufacturers and customers monthly or quarterly. Reportedly, approximately 50% of DRAM demand comes from PCs and servers, while around 35% comes from smartphones.

The report indicated that the demand for HBM, essential for generative AI, is rapidly increasing, and market expectations for the production trend of HBM are expected to boost future DRAM price increases.

A source cited in the report, which is an Electronic product trader, noted that some major manufacturers have accepted the memory manufacturers’ price hike requests. A PC manufacturer source cited by the report also stated that DRAM wholesale prices from April to June are expected to rise by 5-10% compared to January to March.

Another source cited by the report stated that the facilities required to produce HBM are approximately three times larger than those needed for producing general DRAM. If HBM production increases, the production volume of other DRAMs will decrease, thereby driving up prices. Another source cited in the report stated that supply cannot keep up with demand, and pricing power is currently in the hands of memory manufacturers.

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• [News] Samsung and SK Hynix Urgently Reallocate 20% of DRAM Production Capacity to Support Rising HBM demand
• [News] Three-way Contest for HBM Dominance, Uncertainties Surrounding China’s Supply Chain Involvement

(Photo credit: SK Hynix)

As the era of AI advances, following NVIDIA’s application to the Ministry of Economic Affairs (MOEA) for the “A+ Industrial Innovative R&D Program,”  which led to the establishment of the first R&D center in Asia and the creation of Taiwan’s largest AI supercomputer, “Taipei-1”, American AI chip giant AMD is set to follow suit.

According to a report from UDN, AMD plans to invest NTD 5 billion (roughly USD 155 million) to establish an R&D center in Taiwan and intends to apply for the A+ Industrial Innovative R&D Program from the MOEA, highlighting Taiwan’s critical role in AI chip design and manufacturing.

The MOEA has confirmed that AMD applied for the A+ Industrial Innovative R&D Program subsidy at the end of 2023. However, the funding for the program has already been exhausted. Therefore, funds must be allocated in the fifth phase of the A+ Industrial Innovative R&D Program, with the science and technology budget to be set for 2025.

This budget allocation must be approved by the new government administration. Additionally, MOEA officials stated that AMD must submit a concrete plan and gain approval from a review committee established by the Industrial Technology Department of the MOEA.

Previously, the MOEA’s substantial subsidies to global companies under the A+ Industrial Innovative R&D Program sparked mixed reactions within the industry. Some prominent local IC design companies criticized the MOEA, arguing that supporting global companies leads to competition against local businesses and drains valuable local R&D talent.

To avoid controversy, the MOEA has set forth four specific requirements for AMD.

First, they hope AMD will collaborate with Taiwanese IC design companies. Second, any AI servers developed should be manufactured in Taiwan. Third, at least 20% of the R&D workforce should be sourced from abroad, and high-level executives should be stationed in Taiwan. Fourth, AMD should partner with Taiwanese universities to cultivate talent jointly. The MOEA reports that AMD’s response has been very positive, and a thorough review of the application will take place in the second half of the year.

To date, the MOEA’s A+ Industrial Innovative R&D Program has approved subsidies only for two global companies, Micron and NVIDIA, providing them with NTD 4.722 billion (USD 146.48 million) and NTD 6.7 billion (USD 207.8 million), respectively. The MOEA believes this strategy helps solidify Taiwan’s competitive edge in the global semiconductor and AI sectors.

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• [News] Qualcomm Commits to USD 700 Million Investment in Taiwan Over 5 Years in Settlement with Fair Trade Commission
• [News] AI Chip Alone Can’t Hold Up? AMD’s Fiscal Forecast This Quarter Reportedly Falls Short of Expectations

(Photo credit: AMD)

The world’s four major CSPs (Cloud Service Providers) – Microsoft, Google, Amazon, and META – are continuously expanding their AI infrastructure, with their combined capital expenditures projected to reach USD 170 billion this year. According to the industry sources cited in a report from Commercial Times, it’s pointed out that due to the surge in demand for AI chips and the increased area of silicon interposers, the number of chips that can be produced from a single 12-inch wafer is decreasing. This situation is expected to cause the CoWoS (Chip on Wafer on Substrate) production capacity under TSMC to remain in short supply.

Regarding CoWoS, according to TrendForce, the introduction of NVIDIA’s B series, including GB200, B100, B200, is expected to consume more CoWoS production capacity. TSMC has also increased its demand for CoWoS production capacity for the entire year of 2024, with estimated monthly capacity approaching 40,000 by the year-end, compared to an increase of over 150% from the total capacity in 2023. A possibility exists for the total production capacity to nearly double in 2025.

However, with NVIDIA releasing the B100 and B200, the interposer area used by a single chip will be larger than before, meaning the number of interposers obtained from a 12-inch wafer will further decrease, resulting in CoWoS production capacity being unable to meet GPU demand. Meanwhile, the number of HBM units installed is also multiplying.

Moreover, in CoWoS, multiple HBMs are placed around the GPU, and HBMs are also considered one of the bottlenecks. Industry sources indicate that HBM is a significant challenge, with the number of EUV (Extreme Ultraviolet Lithography) layers gradually increasing. For example, SK Hynix, which holds the leading market share in HBM, applied a single EUV layer during its 1α production phase. Starting this year, the company is transitioning to 1β, potentially increasing the application of EUV by three to four times.

In addition to the increased technical difficulty, the number of DRAM units within HBM  has also increased with each iteration. The number of DRAMs stacked in HBM2 ranges from 4 to 8, while HBM3/3e increases this to 8 to 12, and HBM4 will further raise the number of stacked DRAMs to 16.

Given these dual bottlenecks, overcoming these challenges in the short term remains difficult. Competitors are also proposing solutions; for instance, Intel is using rectangular glass substrates to replace 12-inch wafer interposers. However, this approach requires significant preparation, time, and research and development investment, and breakthroughs from industry players are still awaited.

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• [News] TSMC’s Advanced Packaging Capacity Fully Booked by NVIDIA and AMD Through Next Year
• [Insights] Big Four CSPs Continue to Shine in Q1 2024 Financial Reports, AI Returns Garnering Attention

(Photo credit: NVIDIA)