Fab inventories have declined for two consecutive quarters, indicating that reducing excess stock may currently be the semiconductor industry’s top priority. According to industry sources cited in a report from Commercial Times, fabs are predicted to wait until the second half of 2024 to resume ordering silicon wafers.

According to the latest quarterly analysis report from SEMI, a major microelectronics association, global silicon wafer shipments in the first quarter of 2024 reached 2,834 million square inches (MSI), marking a 5.4% decrease from the previous quarter and a 13.2% decrease from the same period last year.

SEMI attributes this decline in silicon wafer shipments to the continuing decline in IC fab utilization and inventory adjustments. Consequently, shipments of silicon wafers of all sizes experienced negative growth in the first quarter of 2024.

Industry sources cited by the same report note that, based on recent trends in foundry orders, apart from TSMC, other semiconductor manufacturers have seen capacity utilization rates around 70%. Among these, DRAM and Flash memory wafer shipments have shown year-on-year increases of 20.3% and 1%, respectively, indicating better performance compared to previous periods.

Japanese silicon wafer manufacturer Sumco recently announced in its financial report that in the first quarter, overall demand for 12-inch silicon wafers had bottomed out. Demand for logic chips used in AI and DRAM had increased. However, for applications outside of AI, customers continued to adjust their production.

Sumco estimates that due to customer production adjustments and the recovery of silicon wafer demand, it may take until the second half of 2024 for the situation to improve.

Industry sources cited by Economic Daily News believe that most IC design companies have returned to normal days of inventory (DOI) and are prioritizing urgent orders for foundries. However, the inventory levels of fabs and memory fabs remain historically high, so they will primarily focus on digesting existing long-term contracts (LTA) in the short term.

Read more

• [News] Silicon Wafer Long-Term Contracts Unstable, Major Foundry Seeks Price Cut from Japanese Suppliers

(Photo credit: TSMC)

Paul de Bot, President of TSMC Europe, confirmed during a seminar in the Netherlands on May 14th that TSMC will start construction of its first chip plant in Europe in Dresden, eastern Germany. The project is scheduled to commence in the fourth quarter of this year, with production expected to begin in 2027.

Last August, TSMC announced the joint venture factory project in Germany, with a total investment of USD 11 billion. Apart from TSMC, Infineon, NXP, and Bosch each holds a 10% stake.

According to a report from Reuters, Kevin Zhang, Senior Vice President of Business Development and Overseas Operations Office at TSMC, stated that the project has received strong support from the European Union and the German government, thus TSMC is confident in obtaining subsidies under the European Chips Act.

Kevin Zhang stated that the semiconductor ecosystem in Europe is currently exciting, indicating that setting up a foundry in Germany would allow TSMC to directly access its major automotive customers.

It is understood that TSMC’s fab in Germany will initially focus on the 22-nanometer process, mainly producing automotive microcontrollers. There is a possibility of expanding to produce more advanced chips in the future.

In addition, Intel, another semiconductor giant, had also planned a significant investment of EUR 30 billion for constructing two new fabs in Magdeburg, Eastern Germany.

TSMC’s global expansion has reached locations in China, the United States, Japan, and Germany, solidifying its goal of being a “long-term and trustworthy provider of technology and capacity.”

TSMC’s Kumamoto Plant in Japan held its opening ceremony in February, with mass production expected to begin in the fourth quarter. Kevin Zhang also emphasized that TSMC will continue to expand its operations in Japan.

In response to growing customer demand, TSMC announced in February plans to begin construction of its Kumamoto Fab 2 by the end of the year, which will be its second, more advanced fab in Japan, scheduled to start operations by the end of 2027.

In contrast, the construction progress of its Arizona plant in the United States has been relatively slow. Due to the delay in the first phase’s production timeline from the end of 2024 to the first half of 2025, the production schedule for the second phase will also be postponed to start after 2027.

Read more

• [News] Latest Overview on TSMC’s Global Expansion Initiatives
• [News] Kumamoto Vying for TSMC’s Third Fab, Looking to Build Semiconductor Hub

NOR Flash manufacturer Wuhan Xinxin Semiconductor Manufacturing Co. (XMC) recently disclosed an IPO counseling filing with the Hubei Securities Regulatory Bureau, according to the official website of the China Securities Regulatory Commission. Its recently announced bidding project may indicate its ambition to become China’s first HBM foundry, according to the report by Chinese media Semi Insights.

As per information from its website, XMC provides 12-inch foundry services for NOR Flash, CIS, and Logic applications with processes of 40 nanometers and above. Originally a wholly-owned subsidiary of Yangtze Memory Technologies (YMTC), XMC announced in March its first external financing round, increasing its registered capital from approximately CNY 5.782 billion to about CNY 8.479 billion. Its IPO counseling filing also indicates that it is still majority-owned by YMTC, with a shareholding ratio of 68.1937%.

According to market sources cited in the same report, XMC’s initiation of external financing and IPO plan is primarily aimed at supporting the significant expansion during a crucial development phase for YMTC. Given the substantial scale of YMTC, completing an IPO within three years poses challenges. Therefore, XMC was chosen as the IPO entity to enhance financing channels.

It is noteworthy that XMC also announced its latest bidding project on HBM (High Bandwidth Memory) – related advanced packaging technology R&D and production line construction, according to local media.

The project indicates the company’s capability to apply three-dimensional integrated multi-wafer stacking technology to develop domestically produced HBM products with higher capacity, greater bandwidth, lower power consumption, and higher production efficiency. With plans to add 16 sets of equipment, XMC’s latest project aims to achieve a monthly output capacity of over 3000 wafers (12 inches), showing its ambition of becoming China’s first HBM foundry.

On December 3, 2018, XMC announced the successful development of its three-dimensional wafer stacking technology based on its three-dimensional integration technology platform. This marks a significant advancement for the company in the field of three-dimensional integration technology, enabling higher density and more complex chip integration.

Currently, XMC has made much progress in the research and development of three-dimensional integrated multi-wafer stacking technology, which has been evident in the successful development of three-wafer stacking technology, the application of three-dimensional integration technology in back-illuminated image sensors, advancements in HBM technology research and industrialization efforts, as well as breakthroughs in the 3D NAND project.

Read more

• [News] China’s Chip Production Surges by 40% in Q1
• [News] Three-way Contest for HBM Dominance, Uncertainties Surrounding China’s Supply Chain Involvement

(Photo credit: XMC)

On May 9th, China’s leading semiconductor foundry, SMIC International, announced its financial report for the first quarter of this year. It revealed a revenue of USD 1.75 billion, a year-on-year increase of 19.7%, and a net profit of USD 71.8 million, marking a significant 68.9% decrease compared to the same period last year, falling below market expectations of USD 76.8 million.

According to its financial data, SMIC’s gross profit margin for the first quarter of this year was 13.7%, not only lower than the 16.4% in the fourth quarter of 2023 but also significantly lower than the 20.8% in the first quarter of 2023.

Per a report from Economic Daily News, SMIC’s management stated that global customer’s willingness for restocking had increased in the first quarter, with the company shipping 1.79 million 8-inch equivalent wafers, a 7% increase from the previous quarter. The capacity utilization rate reached 80.8%, up 4 percentage points from the previous quarter.

For the second quarter of this year, SMIC estimates that the early pull-in demand from some customers is still ongoing, with the company giving revenue guidance of a 5% to 7% increase from the previous quarter. With the expansion of production capacity, depreciation is increasing each quarter, the gross margin guidance is between 9% and 11%.

SMIC further indicated that, assuming no significant changes in the external environment for the full year, the company’s goal is for sales revenue growth to exceed the industry average.

In addition, China’s second-largest semiconductor foundry, Hua Hong, also released its first-quarter financial report, with revenue of CNY 3.297 billion, a year-on-year decrease of 24.62%, and a net profit of CNY 220 million, a year-on-year decrease of 78.76%.

Hua Hong estimates that its main business for the second quarter of 2024 will be between USD 470 million and 500 million, with a gross margin of approximately 6% to 10% for its main business.

Regarding the development of China’s foundry industry, TrendForce previously reported that from 2023 to 2027, propelled by policies and incentives promoting local production and IC development, China’s mature process capacity is anticipated to grow from 29% this year to 33% by 2027. Leading the charge are giants like SMIC, HuaHong Group, and Nexchip. Globally, the ratio of mature (>28nm) to advanced (<16nm) processes is projected to hover around 7:3.

Read more

• [News] Sales Decline Leads to Sharp Profit Drop for SMIC in 2023
• [News] SMIC’s Net Profit Halved Last Year, Faces Further Reductions This Year

(Photo credit: SMIC)

Intel has secured its supply of the new High-NA EUV (high-numerical aperture extreme ultraviolet) lithography equipment from ASML, which the semiconductor heavyweight will allegedly use on its 18A (1.8nm) and 14A (1.4nm) nodes, according to reports from TheElec and Wccftech.

According to sources cited by TheElec, the Dutch fab equipment maker is manufacturing five units of the kit this year, which will all go to Intel, while Samsung and SK Hynix are expected to wait until the second half of 2025 to obtain the aforementioned equipment.

For companies aiming to produce 2-nanometer chips, High-NA EUV lithography equipment may be critical, with each unit priced at over 5 trillion Korean won (approximately US$ 370 million), indicating Intel’s total investment on ASML’s first batch of High-NA EUV kits may amount to US$ 2 billion, according to TheElec and Wccftech.

Intel has confirmed in mid-April that it has received and assembled the industry’s first High-NA EUV lithography system, which is expected to be able to print features up to 1.7x smaller than existing EUV tools. This will enable 2D feature scaling, resulting in up to 2.9x more density.

Compared to 0.33NA EUV, High NA EUV (or 0.55NA EUV) can deliver higher imaging contrast for similar features, which enables less light per exposure, thereby reducing the time required to print each layer and increasing wafer output.

Intel expects to use both 0.33NA EUV and 0.55NA EUV alongside other lithography processes in developing and manufacturing advanced chips, starting with product proof points on Intel 18A in 2025 and continuing into production of Intel 14A.

According to TSMC’s press release in late April, A16, TSMC’s next technology on its roadmap which will combine its Super Power Rail architecture with nanosheet transistors, is scheduled for production in 2026. However, citing Kevin Zhang, TSMC’s senior vice president of business development, Reuters reported that TSMC does not believe it needs to use ASML’s new High-NA EUV lithography tool machines to build the A16 chips.

(Photo credit: ASML)