Wafer foundries’ mature process continues to suffer from oversupply, facing further price reduction pressure. According to a report from Economic Daily News, industry sources from IC design companies revealed that in this quarter, prices for certain mature processes have dropped by single-digit percentages (1% to 3%). Given the current situation, prices in the third quarter may drop by another 1% to 3%, leading to a continuous correction in overall price trends starting from the third quarter of 2022, marking the ninth consecutive quarterly decline.

Industry sources cited by the same report pointed out that this wave of price reductions in mature process was triggered by Chinese foundries two to three years ago, with Taiwanese manufacturers subsequently following suit. Major Taiwanese foundries involved in mature processes, include UMC, Vanguard International Semiconductor (VIS), and PSMC, have all been closely monitoring the latest market changes.

Regarding rumors of further price cuts in the market, UMC stated that the company would not make further comments. VIS, on the other hand, mentioned during a recent earnings call that the price pressure from Chinese foundries has affected its operations, but the company will not engage in these price-cutting competitions. It is expected that as market inventory adjustments approach completion, prices should gradually stabilize without significant fluctuations. PSMC indicated that they have not particularly felt any price pressure.

Local foundries stated that even though customers from specific applications, including driver ICs and other IC design houses, turn to Chinese foundries in order to enjoy cheaper manufacturing prices, they will not engage in price-cutting. After all, price wars may never see an end. Instead, Taiwanese foundries will continue to increase orders from other applications to gradually boost capacity utilization rates.

In the third quarter of 2022, as market conditions reversed, Chinese foundries initiated price cuts, prompting some Taiwanese manufacturers to make slight concessions in pricing. The pricing gap between Chinese and Taiwanese foundries generally remained at double-digit percentages.

To cope with a period of market inventory adjustment, some foundries are more flexible in negotiations, while others hope for customers to “exchange volume for price.”

Overall, foundry pricing has experienced eight consecutive declines up to this quarter. However, with no significant recovery in most end-demand sectors, IC design companies assess that foundry pricing in the third quarter may continue to trend downward.

Industry sources cited by the report believe that Chinese foundries receive official subsidies, allowing them to disregard profit considerations. Previously, IC design houses’ price negotiations with Chinese foundries were mostly successful, which results in single-digit percentage price reductions recently. However, after the third quarter, the room for further price reductions may diminish, indicating that the price seems to be soon hit the bottom.

However, fin order to cope with the current macroeconomic fluctuations, some IC design companies mentioned that after suffering from being “burned” by high inventory in the past, they now tend to wait for clear demand from customers before starting production. In recent years, the proportion of production sent to Chinese foundries has been increasing due to cost considerations. With the continuous expansion of mature process capacity in Chinese foundries, the pressure of oversupply may persist for a while longer.

According to TrendForce’s previous report on the fourth quarter of 2023, global semiconductor foundry revenue rankings showed that the top three semiconductor foundries globally were TSMC, Samsung, and GlobalFoundries, which are all less exposed to mature nodes.

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(Photo credit: TSMC)

Samsung Electronics and Synopsys jointly announced that the former has successfully taped out its first mobile system-on-chip (SoC) with its 3nm gate-all-around (GAA) process. According to Synopsys, Samsung used the Synopsys.ai EDA suite to help with the SoC’s layouts as well as design verification, to enhance its performance.

While it is important that Samsung utilized the Synopsys.ai suite for developing high-performance SoCs, it is also momentous progress as the semiconductor heavyweight finally tapes out its advanced smartphone APs with the node.

The unnamed high-performance mobile SoC from Samsung adopts a universal CPU and GPU architecture, along with various IP modules from Synopsys. The design team not only leveraged the Synopsys.ai EDA suite for fine-tuning designs, but the Synopsys DSO.ai to maximize its output. In addition, Samsung also targeted to achieve higher performance, lower power consumption, and optimized chip area (PPA) by leveraging Synopsys’ Fusion Compiler RTL-to-GDSII solution.

Although Samsung’s foundry has been using the GAA-based SF3E node for chip production over the past two years, it has never been used to produce chips in its own smartphones, nor on other SoCs. So far, the SF3E node has only been utilized for cryptocurrency mining chips, possibly due to the initially low yields of GAAFET nodes.

Though Samsung’s press release only indicates that this SoC has been produced with GAA nodes, and the company possesses more complex SF3 processes in addition to the first generation 3-nanometer SF3E, it is reasonable to speculate that it is SF3 given the timeline.

Kijoon Hong, vice president of SLSI at Samsung Electronics, stated that the company’s long-term collaboration with Synopsys enables leading SoC designs, showcasing the highest performance, power efficiency, and chip area on advanced mobile CPU cores and SoC designs. The tape out represents an important milestone, as it demonstrates how AI-driven solutions can help realize goals. With the help of the most advanced GAA transistor architecture, ultra-high-yield design systems can be established.

This SoC chip achieves a maximum clock speed increase of 300MHz and a 10% reduction in power consumption. Samsung’s SoC development team also utilized techniques such as design partitioning optimization, multi-source clock synthesis (MSCTS), and intelligent routing optimization to reduce signal interference, while other simpler layering methods have also been employed. According to official statements, with the boost of the Synopsys Fusion Compiler, the development process could skip weeks of ‘manual’ design time.”

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(Photo credit: Samsung)

TSMC unveiled its angstrom-class A16 advanced process during the Company’s 2024 North America Technology Symposium on April 25, set to be mass-produced in 2026. Not only is this earlier than competitors like Intel’s 14A and Samsung’s SF14, both slated for 2027 production, but TSMC also emphasized that the A16 does not require the use of High-NA EUV, making it more cost-competitive.

TSMC’s A16 to Lead Competitors in Production Time and Cost

According to TSMC, the A16 advanced process, combining Super PowerRail and nanosheet transistors, is set for mass production in 2026. Super PowerRail relocates power networks to the backside of wafers, freeing up more space on the frontside for signal networks, enhancing logic density and performance. This is ideal for High-Performance Computing (HPC) products with complex signal routing and dense power networks.

Compared to TSMC’s N2P process, the A16 offers an 8% to 10% speed increase at the same Vdd (operating voltage), a 15% to 20% reduction in power consumption at the same speed, and a density increase of up to 1.1 times, supporting data center products.

Photo credit: TSMC

Additionally, as AI chip companies are eager to optimize designs to leverage the full potential of TSMC’s processes, as per a report from Reuters, TSMC doesn’t believe that ASML’s latest High-NA EUV is necessary for producing A16 process chips.

Furthermore, TSMC showcased the Super Power Rail architecture, slated to be operational in 2026, which delivers power from the backside of the chip, aiding in the accelerated operation of AI chips.

Intel 14A Extends ‘5 Nodes in 4 Years’ Strategy

In February, Intel unveiled its 14A process, which would be after its “5 Nodes in 4 Years” strategy. After integrating High-NA EUV production, Intel 14A is expected to improve energy efficiency by 15% and increase transistor density by 20% compared to Intel 18A.

The enhanced version, Intel 14A-E, will further boost energy efficiency by 5% based on Intel 14A. According to the plan, Intel 14A is set for mass production as early as 2026, while Intel 14A-E is slated for 2027.

Photo credit: Intel

Intel recently announced the completion of the industry’s first commercial High-NA EUV lithography tool assembly. The ASML TWINSCAN EXE:5000 High-NA EUV lithography tool is undergoing multiple calibrations and is scheduled to be operational in 2027 for Intel’s 14A process.

Intel emphasizes that when the High-NA EUV lithography tool is combined with its other leading process technologies, it reduces print size by 1.7 times compared to existing EUV machines. This reduction in 2D dimensions increases density by 2.9 times, aiding Intel in advancing its process roadmap.

Samsung SF1.4 Enhances Performance and Power Efficiency with Nanosheet Addition

Photo credit: Samsung

Compared to TSMC and Intel, Samsung’s progress in the angstrom era seems somewhat lagging. Two years ago at the Samsung Foundry Forum 2022, Samsung unveiled its advanced process roadmap, with the angstrom-level SF1.4 (1.4 nanometers) set for mass production in 2027.

Last October, Samsung’s Vice President of Foundry, Jeong Gi-Tae, reportedly told the Korean media outlet The Elec that Samsung has announced its upcoming SF1.4 (1.4-nanometer class) process technology, which would increase the number of nanosheets from 3 to 4. This move is expected to bring significant benefits in chip performance and power consumption

Samsung announced the mass production of SF3E (3nm GAA) in June 2022, introducing a new Gate-All-Around (GAA) architecture. This year, they unveiled the second-generation 3nm process, SF3 (3nm GAP), utilizing the second-generation Multi-Bridge Channel Field Effect Transistor (MBCFET) to optimize performance based on the SF3E foundation.

Additionally, they introduced the performance-enhanced SF3P (3GAP+), suitable for manufacturing high-performance chips. By 2025, Samsung plans to scale up production of the SF2 (2nm) process, followed by mass production of the SF1.4 (1.4nm) process in 2027.

Reportedly, Samsung aims to increase the number of nanosheets per transistor to enhance drive current and improve performance. More nanosheets allow higher current to pass through the transistor, enhancing switching capability and operational speed.

Moreover, more nanosheets offer better control over current, helping to reduce leakage and lower power consumption. Improving current control means transistors generate less heat.

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With the semiconductor market facing uncertainties and limited signs of industry recovery in the first half of 2024, foundries in China, Taiwan, and South Korea are all implementing price reductions to secure orders and solidify customer relationships.

According to TechNews citing from supply chain sources, Samsung Foundry, which had not taken action previously, is expected to follow suit with price cuts in the first quarter to keep pace with competitors.

Reportedly, industry sources suggest that Samsung Foundry is adopting a price reduction strategy in the first quarter of 2024, offering discounts ranging from 5% to 15% and expressing a willingness to negotiate.

Samsung Foundry’s actions can be interpreted as a goodwill gesture towards its customers. The company has been in constant competition with TSMC, especially in processes below 5nm, and actively engaging in negotiations with customers, seeking collaboration opportunities with Qualcomm, NVIDIA, AMD and others.

Considering the subdued semiconductor market in 2023, fabs in both China and South Korea have implemented price cuts to secure orders. The price reductions for mature processes in 8-inch and 12-inch wafer reached 20-30%, while Taiwanese fabs have also made concessions in pricing.

TSMC, the leading foundry, had already been reported to offer price concessions in 2023, with the major focus on mask costs rather than foundry services. It was mentioned at that time that TSMC’s price concessions primarily applied to the 7nm process, where utilization rates were lower, and the extent of concessions depended on the volume of orders from customers.

In terms of the global foundry landscape, according to data published by TrendForce, Taiwan holds approximately 46% of global foundry capacity, followed by China (26%), South Korea (12%), the US (6%), and Japan (2%).

However, due to government incentives and subsidies promoting local production in countries like China and the US, the semiconductor production capacities of Taiwan and South Korea are projected to decrease to 41% and 10%, respectively, by 2027.

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(Photo credit: Samsung)

Taiwanese Semiconductor testing and packaging giant ASE announced today that its subsidiary, ASE Semiconductor, will lease the plant in Nanzih, Kaohsiung, owned by Taiwan’s ASE Test Inc., to expand its packaging capacity.

In the announcement, ASE Holdings revealed that ASE Semiconductor would lease a plant in Nanzih District, Kaohsiung, from its subsidiary ASE Test Inc. The total floor area of the building is approximately 15,600 square meters, with an estimated total usage rights asset value of NTD 742 million (approximately USD 23.8 million).

ASE Holdings stated that the primary purpose of this move is to optimize the overall planning and efficient utilization of plant space within the group, as well as to expand ASE’s packaging capacity.

According to CNA’s report, industry sources believe that ASE’s primary objective with this expansion is to enhance its production capacity for advanced packaging of Artificial Intelligence (AI) chips, but it is not directly related to CoWoS packaging.

Market insiders point out that ASE Holdings has been collaborating with foundry on technologies related to advanced packaging interposers and has CoWoS solutions. The earliest expected time for mass production is by the end of this year or early next year.

Reportedly, according to data, ASE’s Kaohsiung plant contributes to approximately 20% of ASE Holding’s overall revenue. The plant primarily provides services such as packaging, wafer bumping and probing, materials, and final testing.

The Kaohsiung plant is also establishing several smart plants, focusing on high-end processes, including Fan-Out packaging, System-in-Package (SiP), wafer bumping, and FlipChip packaging. These technologies find applications in various fields, including automotive, medical, IoT, high-speed computing, artificial intelligence, and application processors.

ASE actively positions itself in various advanced packaging technologies. Notably, the Fan-Out Chip on Substrate with Bridge (FOCoS-Bridge) packaging technology integrates multiple Application-Specific Integrated Circuits (ASICs) and High Bandwidth Memory (HBM), targeting the customized AI chip advanced packaging market.

In addition, ASE Semiconductor has introduced a cross-platform integrated design tool that combines several advanced packaging technologies, addressing the demands of advanced packaging for AI chips.

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(Photo credit: ASE)