Intel CEO Pat Gelsinger has discussed around Intel’s process status, comparisons with TSMC in a recent interview. According to Barron’s report, Gelsinger mentioned in the interview that Intel’s 18A process and TSMC’s N2 process seem comparable, with no significant advantage for either of them.

However, Gelsinger claimed that, ‘But the backside power delivery, everybody says Intel, score.’ He further stated, ‘it gives better area efficiency for silicon, which means lower cost. It gives better power delivery, which means higher performance.’

Gelsinger mentioned that good transistor and great power delivery make 18A a little bit ahead of N2. Besides, TSMC has given a very high-cost envelope, where Intel can fit underneath to be margin accretive.

In fact, not only TSMC and Intel, but also including Samsung, the three semiconductor manufacturing giants are actively positioning themselves in the increasingly competitive field of advanced process technology.

At the recent IEEE International Electron Devices Meeting (IEDM), Intel, TSMC, and Samsung each showcased their CFET (Complementary FET) transistor solutions. The stacked CFET transistor architecture involves stacking two types of transistor -nFETs and pFETs- together, aiming to replace Gate-All-Around (GAA) and become the next-generation transistor design for doubling density.

As reported by IEEE Spectrum, Intel was the first foundry to showcase the CFET solution, publicly unveiling an early version back in 2020. During the conference, Intel introduced one of the simplest circuits manufactured with CFET, focusing on improvements for an inverter.

The CMOS inverter sends the same input voltage to the gates of two-transistor stacked together, generating an output that is logically opposite to the input, and the inverter is completed on a single fin.

Intel also improved the CFET stack’s electrical characteristics by increasing the number of nanosheets per device from two to three, decreasing the separation between the two devices from 50 nm to 30 nm.

According to the current progress, experts, as indicated by IEEE Spectrum, anticipate that the commercialization of CFET technology on a large scale will likely take another 7 to 10 years from now. Before reaching that stage, there are still many preparatory tasks that need to be completed.

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(Photo credit: Intel)

An increasing number of Chinese semiconductor design companies are seeking collaboration with testing and packaging facilities in Malaysia to carry out advanced chip packaging. According to Reuters’ report, this move aims to hedge the risk of potential expanded U.S. restrictions on the Chinese semiconductor industry.

As there is currently only one non-U.S. testing and packaging provider in Malaysia with advanced capabilities, namely ASE Technology Holding Co., a Taiwanese semiconductor packaging and testing firm, industry sources believe that ASE is likely to become the top choice for orders from Chinese enterprises.

Previously, the U.S. has imposed controls on China’s advanced semiconductor manufacturing processes and access to high-performance chips from major companies like NVIDIA. However, advanced packaging has not yet fallen within the restricted scope.

Two anonymous sources reportedly revealed that some of the Chinese businesses are showing interest in advanced chip packaging services. Despite the fact that the chip packaging sector has not yet faced export controls from the U.S., concerns are rising among businesses due to its involvement in sophisticated technology, fearing that it might be targeted for curbs on exports in the future.

Reuters’ report also indicates that due to the relatively affordable investment costs in Malaysia and the availability of experienced workforce and sophisticated equipment, an increasing number of Chinese chip design firms are seeking Malaysian Firms to carry out advanced chip packaging activities, including graphic processing units (GPUs).

Insiders have informed Reuters that the related contracts only involve packaging and do not violate any restrictions imposed by the U.S.. Additionally, they clarified that wafer manufacturing is not included in these contracts.

Two of the sources mentioned that some contracts have already been agreed. However, these insiders prefer not to disclose the names of the involved companies.

Meanwhile, according to a report from Taiwan’s Economic Daily News, when observing the global landscape of advanced packaging, in addition to TSMC, there are integrated device manufacturers (IDMs) like Intel and Samsung, as well as outsourcing semiconductor assembly and test (OSAT) companies like ASE Technology, Amkor, and others that possess advanced packaging capabilities. Among them, only ASE Technology, Amkor, and Intel have production capacity in Malaysia.

Reportedly, industry analysts predict that Chinese companies seeking advanced packaging support in Malaysia, due to geopolitical considerations, are likely to avoid American companies such as Intel and Amkor. Given that ASE is not an American company and can provide high-end packaging services, it is expected to be the preferred choice for Chinese companies.

ASE has previously stated that it will continue to invest in advanced packaging for AI, expecting the performance of advanced packaging to double next year compared to this year.

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(Photo credit: ASE Holdings)

Following Intel’s move to split its outsourced foundry model, TSMC is gearing up to expand its advanced manufacturing processes in Taiwan, ready to face the competition head-on.

According to China Time’s report, following the equipment first tool-in at the 2nm fab in Baoshan scheduled for April next year, industry sources suggest a high likelihood of the 1.4nm fab being established in the second phase of the Central Taiwan Science Park.

Additionally, TSMC is actively expanding its CoWoS process and considering the construction of its 7th advanced packaging and testing plant in the central region, with Chiayi Science Park and Yunlin actively under consideration.

Semiconductor industry insiders point out that TSMC is beginning to feel the pressure, and this year, founder Morris Chang’s main concern regarding competition has shifted from Samsung to the resurgent Intel.

Starting from the second quarter of next year, Intel, a rival of TSMC, plans to separately disclose financial reports for chip development and Intel Foundry Services (IFS), implementing its internal foundry outsourcing model.

Intel’s move aims to protect the assets and know-how of third-party customers. Coupled with international chip design firms gradually releasing orders to Intel due to diversified supply chain concerns, it shows that Intel’s outsourcing strategy is gradually proving effective.

Intel’s recent successes in foundry processes, including the PowerVia backside power delivery technology, glass substrates and Foveros Direct for advanced packaging.

According to TrendForce’s 3Q23 Ranking of  Global Top10 Foundries by Revenue, Intel’s foundry business has entered the global top 10 for the first time, ranking ninth with the industry’s fastest quarterly growth.

Confronted with growing competition from Intel, TSMC is intensifying its efforts and accelerating the construction of advanced process production capacity. The recent expansion plans are becoming clearer, with the 1.4nm fab likely located in the second phase of the Central Taiwan Science Park, aligning with the ongoing increase in demand for advanced packaging.

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(Photo credit: TSMC)

Rumors suggest TSMC will set up a new fab that deploys 2nm and more advances processes in the Central Taiwan Science Park (CTSP) Phase 2, Taichung City, Taiwan. The city mayor Shiow-Yen Lu has confirmed TSMC’s entry into Phase 2, designating all allocated land exclusively for TSMC 2nd Fab in CTSP. According to the local government, the new fab is expected to house “processes advances than 2nm,” expressing the hope that TSMC will bring its latest technology to Taichung City.

The latest news about TSMC’s new plant has emerged. CNA reported that during the regular session of the Taichung City Council on December 12th, the mayor responded to councilors regarding the progress of Taichung’s efforts to attract TSMC’s new plant. Mayor stated that the city government has secured the deal, confirming that TSMC will establish itself in the CTSP Phase 2.

Mayor Lu explained that due to the immense scale of TSMC’s Taichung 2nd Fab, the Ministry of Economic Affairs in Taiwan is assisting as well. While CTSP Phase 1 accommodates numerous companies, almost all the land in Phase 2 is allocated for TSMC’s Taichung 2nd Fab.

In response, TSMC expressed gratitude for the support from the Taichung city government and pledged to continue cooperating with the relevant procedures. Regarding whether Phase 2 of CTSP will adopt technology for 2nm and more advances process, TSMC did not provide further clarification.

TSMC has also responded to earlier reports about Samsung offering discounts so as to be more effective in competing with TSMC for 2nm orders. During a joint interview before the Taiwan Executive Yuan’s Science & Technology Meeting on December 13th, TSMC Chairman Mark Liu stated that TSMC’s customers prioritize technological quality. As for the outlook for the coming year, Liu expressed hope for a very healthy year.

▲ TSMC’s Current Layout of Global Production Capacity
Edited by TrendForce, November, 2023

(Image: TSMC)

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Nvidia CFO, Colette Kress, recently hinted again that the next-gen chips might be outsourced to Intel Corp. During the call with semiconductor analyst Tim Arcuri at the UBS Global Technology Conference on November 28th, she was asked whether Intel would be considered as a foundry partner for the next-gen chips.

In response, she stated that there are many powerful foundries in the market. TSMC and Samsung Electronics have been great partners. She said, “we’d love to have a third one,” when answering whether Nvidia want a third partner.

Kress also mentioned that, TSMC’s and others’ US fab may also be their options, and “there is nothing necessarily different but again in terms of different region. Nothing will stop us from potentially adding another foundry.”

Kress highlighted that Nvidia’s current data center GPUs designed for AI and high-performance computing (HPC) are predominantly outsourced to TSMC. However, in the previous generation, Nvidia’s gaming GPUs were mainly entrusted to Samsung for fabrication. According to Sedaily, Samsung’s foundry was responsible for manufacturing Nvidia’s GeForce RTX 30 series gaming GPUs based on the Ampere architecture.

Speaking of foundry partners for AI products, Nvidia anticipates that TSMC will remain a crucial foundry partner for producing AI Hopper H200 and Blackwell B100 GPUs. Any additional orders might be entrusted to Samsung.

Nvidia CEO previously said Intel’s next-gen process test chips “look good”

Additionally, reports from Barron also mentioned that on May 30th, during an interaction with journalists in Taiwan, Nvidia CEO Jensen Huang was asked whether Nvidia is considering diversifying its supplier base given the rising tensions between the U.S. and China. In response, Huang referred to Nvidia’s long-standing collaboration with TSMC and Samsung Electronics, stating, “We have a lot of customers depending on us. And so our supply chain resilience is very important to us. We manufacture in as many places as we can.”

At that time, Huang also expressed, “We’re open to manufacturing with Intel. And (Intel CEO) Pat (Gelsinger) has said in the past that we’re evaluating their process, and we’ve recently received the test chip results of their next generation process and the results look good.”

From Nvidia CFO’s talk in November and Nvidia CEO’s response in May, it is obvious that, beyond TSMC and Samsung, Nvidia is thinking about a potential third foundry partner.

(Image: NVIDIA Hopper Architecture – H100 SXM)