Intel and Japan’s National Institute of Advanced Industrial Science and Technology (AIST), under the Ministry of Economy, Trade and Industry, are reportedly planning to set up an R&D hub in Japan. As per a report from Tom’s Hardware, the new facility is expected to be built within the next 3-5 years, with a total investment projected to reach hundreds of millions of dollars.

According to a report from Nikkei on September 3rd, this facility is said to be putting more focus on developing advanced semiconductor manufacturing equipment and materials, as well as introducing Extreme Ultraviolet (EUV) lithography.

On the other hand, the hub will feature EUV lithography equipment, with AIST overseeing operations and Intel providing expertise in semiconductor manufacturing using EUV equipment.

The report from Nikkei indicates that Rapidus, expected to mass-produce 2nm chips by 2027, will introduce Japan’s first EUV lithography equipment in December 2024. The planned R&D hub, per Nikkei, will become the first research institution in Japan to incorporate such tool. The hub is also considering technical collaboration and talent exchange with U.S. research institutions.

Reportedly, EUV lithography equipment is essential for producing advanced chips below 5nm, but each unit costs over JPY 40 billion, making it difficult for materials and equipment manufacturers to purchase independently.

Therefore, semicondcutor companies may have to be rely on certain research institutions’ EUV equipment overseas to conduct research and product development, such as imec.

The global semiconductor foundry leader, TSMC, established a next-generation semiconductor R&D hub in Ibaraki Prefecture, Japan, in June 2022. Additionally, Samsung Electronics plans to set up a chip R&D center in Yokohama, Japan, by the end of 2024.

Read more

• [News] Japan’s Chip Equipment Sales Hit Record High This Year, with 23.6% YoY Growth in July
• [News] Intel Reportedly Utilizes Sharp’s LCD Panel Factory for Semiconductor Backend Process

(Photo credit: Intel)

Reuters previously reported that Intel is considering selling its stake in Altera, a FPGA (Field-Programmable Gate Array) manufacturer, as part of its business restructuring and cost-cutting efforts, as AMD and Marvell are said to be potential buyers.

As per a report from Economic Daily News citing sources, it’s believed that if the sale goes through, a significant portion of Altera’s orders could be redirected to TSMC, which would be highly beneficial for the Taiwanese foundry giant.

The same report indicated that Altera used to be a major customer of TSMC. However, after Intel acquired Altera in 2015, the orders were redirected to Intel. TSMC’s rapid growth, bolstered by orders from clients like Apple, AMD, and NVIDIA, helped mitigate the impact of losing Altera’s business though.

If Altera is no longer part of Intel, as it might be is acquired by companies like AMD or Marvell, which are currently key clients of TSMC, it is likely that Altera’s orders may return to TSMC in significant volumes.

Intel acquired Altera for USD 16.7 billion in 2015, and has previously indicated plans to sell a portion of its stake through an initial public offering (IPO), though no specific date has been set.

Citing sources familiar with the matter, Reuter’s report suggested that Intel’s plan does not currently include splitting up the company or selling its foundry business to buyers like TSMC, Reuters notes.

Intel had already begun segregating its wafer foundry business into an independent division and financials, starting from the first quarter of this year.

Per Reuters, the company has established a wall between its foundry and IC design business to ensure that the design division’s potential customers cannot access the confidential technologies of Intel’s foundry clients.

Read more

• [News] AMD Could Emerge as a Prospective Buyer for Intel’s Potential Sale of Altera
• [News] Intel Reportedly Mulls to Sell FPGA Unit Altera and Freeze USD 32 Billion German Project amid Crisis

(Photo credit: Intel)

In a report by Bloomberg on August 29 citing sources, it’s rumored that Intel Corp. is working with investment bankers to navigate what is described as the most challenging period in its 56-year history.

Reportedly, Intel is said to be exploring various options, including spinning off its product design and foundry businesses, and canceling certain construction plans. Notably, Morgan Stanley and Goldman Sachs have been advising Intel, with merger being one of the options on the table.

Multiple options are expected to be presented at the board meeting in September. According to sources cited by Bloomberg, Intel is unlikely to spin off its foundry business unless absolutely necessary. The company is rumored to favor more moderate approaches, such as delaying certain expansion plans.

Per another report from CNBC, during the Deutsche Bank’s Technology Conference on August 29, Intel CEO Pat Gelsinger acknowledged that the past few weeks have been challenging. He then emphasized that the company is prepared to face the market’s criticism and tackle the challenges ahead.

Gelsinger further mentioned that the surge in AI has led to weaker performance in Intel’s server business, a challenge the company is still working to address. However, he remains optimistic about the future, noting that the finish line is already in sight.

He also mentioned that Intel will soon launch “Lunar Lake,” which he described as the most compelling PC product the company has ever developed.

Intel is currently facing significant challenges. On August 1, the company announced financial results that fell short of Wall Street expectations and revealed plans to cut over 15% of its workforce.

Gelsinger noted that the layoffs would impact approximately 15,000 employees. He acknowledged that Intel’s revenue growth has been below expectations and that the company has not yet benefited from trends like AI. Gelsinger highlighted issues with high costs and low profit margins as well, stating that he never anticipated an easy path ahead.

A report from Reuters also revealed that former Intel board member Lip-Bu Tan has stepped down after just two years. Tan, who was previously the CEO and executive chairman of electronic design automation (EDA) software company Cadence Design Systems Inc..

Read more

• [News] Lip-Bu Tan Resigns from Intel Board Amid Reported Disagreements
• [News] Intel’s Earnings Fall Short, Cutting Over 15% of Workforce

(Photo credit: Intel)

TSMC is set to offer a new round of its CyberShuttle prototyping service in September. According to sources cited in a report from Commercial Times, it’s revealed that, as per usual practice, there are two opportunities each year, in March and September, for customers to submit their projects. It is indicated that the highlight this time is expected to be the 2nm process, providing leading companies with an opportunity to gain an edge.

TSMC’s 2nm technology is progressing smoothly, with the new Hsinchu Baoshan plant on track for mass production next year. Previously, there were rumors indicating that Apple is considering adopting 2nm chips in 2025, with the iPhone 17 series potentially being among the first devices to use them.

Reportedly, both TSMC’s N2P and A16 technologies are expected to enter mass production in the second half of 2026, offering improvements in power efficiency and chip density.

ASIC companies are eagerly participating in CyberShuttle this time, even though customer intentions for the first 2nm tape-out are still unconfirmed. However, this technology will likely maintain TSMC’s leadership in advanced processes, securing its future technological advantage.

CyberShuttle, also known as MPW (Multi-Project Wafer), refers to the process of placing chips from different customers onto the same test wafer. This approach not only allows for the shared cost of photomasks but also enables rapid chip prototyping and verification, enhancing customers’ cost efficiency and operational effectiveness.

Based on TSMC’s official information, the CyberShuttle prototyping service significantly reduces NRE costs by covering the widest technology range (from 0.5um to 7nm) and the most frequent launch schedule (up to 10 shuttles per month), all through the Foundry segment’s most convenient on-line registration system.)

TSMC’s CyberShuttle prototyping service also validate the sub-circuit functionality and process compatibility of IP, standard cell libraries and I/Os, reducing prototype costs by up to 90%. TSMC states that their current CyberShuttle service covers the broadest range of technologies and can offer up to 10 shuttles per month.

TSMC’s 2nm technology is expected to make its debut in September, offering opportunities for test chips.

Per the report from Commercial Times, IC design companies have pointed out that, unlike the familiar FinFET (Fin Field-Effect Transistor) structure, the industry is transitioning to the Gate-All-Around FET (GAAFET) structure, making it crucial for the market to quickly adapt.

This also allows IC design companies to provide related products to end customers, demonstrating their 2nm design capabilities.

ASIC companies have also revealed that, based on CyberShuttle data, the number of advanced process projects below 7nm is relatively small, with mature processes still dominating.

This suggests that future competition will likely focus on a few leading companies. Those who miss the first wave of 2nm technology may fall behind their competitors by up to six months, making securing a spot on the Shuttle even more critical.

Read more

• [News] TSMC Reportedly to Raise 3nm & 5nm Prices Soon, Looking to Maintain Long-Term Profit Margins 
• [News] Apple Not Adopting TSMC 2nm for iPhone 17? A19 Pro Chip Rumored to Use N3P Process

(Photo credit: TSMC)

According to data released by the Semiconductor Equipment Association of Japan (SEAJ) on August 27th, Japan’s semiconductor manufacturing equipment sales continue to soar, with July sales up by about 20%, marking four consecutive months of double-digit growth. Sales from January to July reached a historic high for the period.

Reportedly, the sales of Japan-made chip equipment in July 2024 (based on a 3-month average basis, including exports) reached JPY 348.092 billion, a significant 23.6% increase compared to the same month last year.

This marks the seventh consecutive month of growth and the fourth consecutive month with over 10% growth. Monthly sales have surpassed JPY 300 billion for nine straight months.

Compared to the previous month (June 2024), sales increased by 1.2%, marking the eighth monthly growth in nine months.

From January to July 2024, Japan’s chip equipment sales totaled JPY 2.480115 trillion, a 16.7% increase compared to the same period last year. This figure surpasses the previous record of JPY 2.134268 trillion set in 2022, setting a new all-time high.

The upward trend is in accordance with the observation by Japan’s chip equipment giant Tokyo Electron (TEL) and the Semiconductor Equipment and Materials International (SEMI).

Tokyo Electron (TEL) announced in its August 8 financial report that due to strong investments in AI servers, the 2024 global wafer fab equipment (WFE) market size has been revised upward from the previous estimate of around USD 100 billion (up 5% year-on-year) to over USD 100 billion.

The Semiconductor Equipment and Materials International (SEMI) forecast report released on July 10 predicts that global chip equipment sales in 2024 are estimated to increase by 3.4% year-over-year to USD 109 billion, surpassing the USD 107.4 billion record set in 2022.

Read more

• [News] Booming GPU and HBM Demand Pushes Japanese Chip Equipment Annual Sales to Record High
• [News] Booming Sales of Japanese Semiconductor Equipment Continue to Break Records, Reportedly Surpassing JPY 300 Billion

(Photo credit: TEL)