To continue advancing Moore’s Law, TSMC Chairman and President C.C. Wei personally confirmed that FOPLP (Fan-Out Panel-Level Packaging) is in full swing. According to a report from Commercial Times, TSMC has established an R&D team and production line, currently still in the initial stages. Wei further forecasted that related achievements might be seen within three years.

Additionally, the sources cited by the same report also revealed that TSMC is interested in acquiring Innolux’s 5.5-generation LCD panel plant as well, partnering with Taiwanese companies to tackle new packaging processes. However, TSMC has not confirmed these rumors but emphasized that the company is continuously searching for suitable locations for expansion.

On average, die size continues to grow by 5-10%, reducing the number of chips that can be extracted from a single wafer and further squeezing wafer and advanced packaging capacity. Industry sources cited by Commercial Times believe that converting from wafer-level to panel-level packaging is more cost-effective.

Moreover, in response to Intel’s plan to mass-produce the industry’s first glass substrate technology for next-generation advanced packaging between 2026 and 2030, TSMC has started researching related glass substrate technologies to meet customer demands.

TSMC introduced the FOWLP technology named InFO (Integrated Fan-Out) in 2016, first used in the iPhone 7’s A10 processor. Subsequently, assembly and testing facilities actively promoted FOPLP solutions, looking to attract customers with lower production costs.

Currently, per the sources cited by Commercial Times, InFO has only one customer. Fan-Out packaging is a familiar area for TSMC, and future HPC (high-performance computing) clients like NVIDIA and AMD might adopt next-generation advanced packaging technology, replacing existing materials with glass substrates.

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(Photo credit: TSMC)

With the surge in new applications like AI, advanced packaging remains a hot topic, particularly with FOPLP (Fan-Out Panel Level Packaging) technology gaining renewed attention. According to sources cited by a report from MoneyDJ, leading semiconductor foundry TSMC has officially formed a team, currently in the “Pathfinding” phase, and is planning to establish a mini line with a clear goal of advancing beyond traditional methods.

TSMC introduced the FOWLP (Fan-Out Wafer Level Packaging) technology named InFO (Integrated Fan-Out) in 2016, first used in the iPhone 7’s A10 processor. Subsequently, assembly and testing facilities actively promoted FOPLP solutions, looking to attract customers with lower production costs, yet faced ongoing technical challenges. Therefore, current terminal applications remain within mature processes, such as PMIC (Power Management IC) products.

However, per the sources cited by the same report, TSMC’s move to transition advanced packaging technology from wafer level to panel level is more than just talk—it’s becoming a reality. It is reported that TSMC is planning to use rectangular substrates measuring 515mm by 510mm, with a dedicated team already conducting research and planning to establish a mini line.

The source further mentioned that, TSMC’s development of FOPLP can be seen as a rectangular version of InFO, offering advantages such as lower unit costs and larger package sizes.

This advancement could further integrate other technologies on TSMC’s 3D fabric platform, paving the way for 2.5D/3D advanced packaging solutions to serve high-end product applications. This approach could be regarded similar to a rectangular CoWoS, currently targeted at the AI GPU sector with NVIDIA as a customer. If progress continues smoothly, these developments could potentially debut between 2026 and 2027.

On the AMD front, it is understood that their initial partners for FOPLP are ASE Technology and PowerTech Technologies, with potential applications in PC or gaming console chips. Reportedly, it’s suggested that previous packaging methods for PCs and gaming consoles primarily used FC-BGA, but upcoming new products may potentially upgrade to CoWoS level.

Sources cited by the report note that in the early stages of FOPLP, players like PowerTech Technologies, Innolux, and ASE Technology faced challenges and intermittent demand. To allocate resources effectively, equipment suppliers have been conservative in their investments in related fields, focusing mainly on adjusting specifications to meet customer demands. With TSMC now officially joining, equipment suppliers are shifting to a more proactive stance in preparation for upcoming developments.

In summary, the development of the FOPLP ecosystem hinges largely on TSMC’s role. TSMC is expected to maintain leadership in the high-end segment, while packaging and testing firms will cater to the mid-to-high-end markets. Semiconductor experts believe that in the realm of high-speed computing, CoWoS will remain mainstream for the next 3 to 5 years, with advanced 3D packaging like SoIC gaining prominence in high-end applications, solidifying TSMC’s position as a key player.

For packaging and testing companies, the key lies in product upgrades that offer cost-effectiveness. The success of FOPLP as the next generation of advanced packaging hinges on how chip manufacturers position their products, address yield issues related to warpage, and ensure overall performance and pricing that justify customer investment.

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(Photo credit: TSMC)

Global semiconductor giants are concentrating their R&D efforts on advanced packaging technologies to drive performance enhancements. According to a report from Commercial Times, as packaging technology progresses from 2.5D to 3D, chip stacking technologies have become a showcase for the competitive prowess of major companies.

“Hybrid Bonding” is seen as the key technology for future chip connections. In addition to international companies like Applied Materials and Besi actively positioning themselves, Taiwanese companies led by TSMC, including Gallant Micro, MPI Corporation, E&R Engineering Corporation, C SUN, Saultech, and Grand Process Technology, are also developing and seizing opportunities in Hybrid Bonding.

The report also cited industry sources, pointing out that Grand Process Technology has been supplying TSMC since the inception of InFO (Integrated Fan-Out Packaging). It is revealed that Grand Process Technology is also actively participating in future SoIC (System on Integrated Chips) advanced packaging, focusing on wafer cleaning and photoresist removal in etching processes.

It is indicated by the report that Grand Process Technology’s capacity will be operating at full speed until the first quarter of next year, with lead times extended to nine months. Last year’s orders are currently being installed gradually, with most concentrated on advanced packaging.

Semiconductor equipment manufacturer C SUN and its investment company Gallant Micro are currently investing in Hybrid Bonding-related equipment. C SUN primarily focuses on developing the best solutions for permanent bonding to enhance yield rates. Meanwhile, Gallant Micro leverages its relative advantage in chip sorting machines within its product line.

MPI Corporation, a testing interface vendor, has also entered the initial stages of inspection and analysis for Hybrid Bonding processes. Development of related products is nearing completion.

E&R Engineering Corporation also emphasizes that its top-tier plasma cleaning equipment is currently aimed at achieving high cleanliness of bonding surfaces to enhance adhesion.

Saultech Technology holds a positive outlook on the future market trends of Hybrid Bonding as well. The company has introduced equipment that corresponds to both Hybrid Bonding and Fan-Out technologies. Saultech has independently developed key technologies including bonding and die cleaning processes.

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(Photo credit: Applied Materials)

The semiconductor industry, driven by AI, is entering a new upward cycle. According to a forecast report from SEMI, after the trough in 2023, the total sales of equipment in 2024 will hit a new high, with growth momentum continuing into 2025. Among this trend, per a report from Commercial Times, major companies including TSMC, Intel, Samsung, SK hynix, and Micron are all actively preparing, with plans to continue increasing capital expenditure next year in preparation for the AI era.

TSMC and Intel are the most proactive foundries. Intel plans to increase its capital expenditure by 2% in 2024, reaching USD 26.2 billion; TSMC’s capital expenditure for this year is expected to be between USD 28 billion and USD 32 billion.

The same report further cited sources, indicating that TSMC’s capital expenditure this year will reach the upper end of the estimated range. Next year, the upper limit is expected to increase by another USD 5 billion to USD 37 billion, potentially reaching the second-highest level in its history.

It’s reported that customer demand for TSMC’s 2nm process capacity has exceeded expectations. In addition to Apple securing the first batch of TSMC’s 2nm capacity, non-Apple customers are also actively planning for advanced processes. TSMC continues to advance its goal of mass production of the 2nm process by next year.

Another source cited by Commercial Times reveals that TSMC accelerated equipment orders in the second quarter and further increased momentum in the third quarter, primarily to ensure the smooth launch of the 2nm process by mid-next year.

In the HBM sector, Samsung and SK hynix are reportedly raising funds to prepare for significant production expansion in 2025.  A report from Korean media outlet Korea Economic Daily (KED) indicated that Samsung Electronics and SK hynix are considering applying for loans from the Korea Development Bank, with planned loan amounts of KRW 5 trillion (roughly USD 3.6 billion) and KRW 3 trillion (roughly USD 2.2 billion), respectively.

Micron’s capital expenditure plan for the 2024 fiscal year is about USD 8 billion. In the fourth quarter of the 2024 fiscal year, Micron will spend approximately USD 3 billion on fab construction and new wafer fab equipment (WFE). For the 2025 fiscal year, Micron plans to significantly increase its capital expenditure, targeting 30% of its revenue, or about USD 12 billion. Earlier, Micron’s Chief Operating Officer, Manish Bhatia, stated that the scale of the HBM business is expected to expand to several billion dollars in the 2025 fiscal year.

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(Photo credit: Micron)

This year, global semiconductor manufacturing equipment sales are expected to grow and set a new historical record. It is estimated that next year will see even more robust growth, with an anticipated increase of 17%.

According to the forecast report from the International Semiconductor Industry Association (SEMI) released on July 10th, it’s indicated that global chip equipment sales in 2024 are estimated to increase by 3.4% year-over-year to USD 109 billion, surpassing the USD 107.4 billion record set in 2022. Furthermore, 2025 is projected to show even stronger growth, with sales expected to surge to USD 128 billion, breaking the record set in 2024.

“The growth in total semiconductor manufacturing equipment sales already underway this year is forecast to be followed by a robust expansion of roughly 17% in 2025,” said Ajit Manocha, SEMI president and CEO. “The global semiconductor industry is demonstrating its strong fundamentals and growth potential supporting the diverse range of disruptive applications emerging from the Artificial Intelligence wave.”

SEMI noted that due to continued strong equipment investment in China and increased investment in DRAM and HBM driven by AI computing, global sales of wafer fab equipment (WFE) in 2024 are estimated to grow by 2.8% year-over-year to USD 98 billion.

This is a significant upward revision from the previous estimate of USD 93 billion made in December and surpasses the USD 96 billion recorded in 2023, setting a new historical high. With the increased demand for advanced logic and memory applications, global WFE sales in 2025 are projected to increase by 14.7% year-over-year to USD 113 billion.

SEMI further stated that until 2025, China, Taiwan, and South Korea are expected to remain the top three countries in chip equipment investment. Due to continued growth in China’s equipment procurement, China is expected to maintain its leading position throughout the forecast period (up to 2025). Equipment shipments to the Chinese market in 2024 are estimated to exceed USD 35 billion, setting a new historical high, solidifying China’s unshakable lead. However, due to large-scale investments in China over the three-year period ending in 2024, it is anticipated that investments will decrease in 2025.

Chip equipment giant Tokyo Electron (TEL) announced in a press release on May 10 that starting in the second half of this year, the demand for DDR5 and HBM will increase, driving a projected recovery in investments in the most advanced DRAM.

As a result, the global market size for front-end chip manufacturing equipment in 2024 is projected to grow by 5% year-on-year to approximately 100 billion USD, matching the current historical high recorded in 2022 (around USD 100 billion). Additionally, with continued growth in AI servers and a recovery in demand for PCs and smartphones, the WFE market is anticipated to see a double-digit increase (over 10%) in 2025 compared to 2024.

In a financial report press release on May 9, semiconductor equipment company Screen Holdings stated that due to investments in mature processes in China and investments in the most advanced processes in Taiwan, the WFE market is expected to grow in 2024, with an estimated annual increase of about 5%.

Per a report by Nikkei on July 5th, SEAJ’s forecast report indicates that for the 2024 fiscal year (April 2024 to March 2025), the sales of Japanese-made chip equipment (including sales by Japanese companies both domestically and overseas) have been increased to JPY 4.2522 trillion, marking a significant increase of 15.0% compared to the 2023 fiscal year.

This will be the first time annual sales break the 4 trillion yen mark, setting a new historical record. The main drivers are the widespread adoption of AI, leading to extremely strong demand for GPUs used in AI servers, and the continued surge in demand for HBM used in conjunction with these GPUs.