According to a report from the Commercial Times, Tokyo Electron (TEL), a leading global semiconductor equipment manufacturer, is the only company in the world that possesses equipment for four consecutive processes: deposition, coating/developing, etching, and cleaning, which are crucial steps before wafers enter the process of EUV lithography. As the semiconductor nodes keep advancing, the Japanese semiconductor giant would significantly benefit from the trend by its extensive product line.

Hiromitsu Kambara, TEL’s President & Representative Director of TEL Miyagi Ltd., stated that as chip design evolves, etching technology is continuously advancing towards 3D development, with vertical stacking making more efficient use of space. However, the increase in the number of stacking layers leads to an increase in the number of deposition cycles and etching times, thereby necessitating the growth in the number of required machines.

While EUV bellwether companies enjoy nearly 100% market share in the sector, TEL, with its close collaboration with the industry leader in the coating/developing process, could also dominate in this field, the report noted. In other words, as EUV shipments increase, TEL will benefit concurrently. TEL also disclosed that it has already established a research and development center in Taiwan and will soon expand its cleanroom facilities to collaborate with the most advanced process manufacturers.

When paired with partner Litho (lithography) machines, TEL has nearly 100% market share in the coating/developing market. Currently, TEL operates in 19 countries with a total of 87 locations, according to Commercial Times.

As the semiconductor industry enters the angstrom era, fabs are increasingly relying on equipment precision, for which TEL has prepared accordingly. TEL’s latest product, Grinder, is designed not only to ensure wafer flatness but also to achieve partial etching flatness and surface cleaning. This allows the equipment to measure wafers’ flatness and cleanliness effectively.

According to a previous report from Nikkei citing sources, TSMC is rumored to be entering the fan-out panel-level packaging sector. As cited in a report from UDN, Intel and Samsung have also announced plans to invest in this area. With TSMC, the leading wafer foundry, joining the fray, the three semiconductor giants are set to compete in fan-out panel-level packaging.

TSMC stated yesterday that the company is closely monitoring the progress and development of advanced packaging technologies, including panel-level packaging technology.

Nikkei reported that in response to future AI demand trends, TSMC is collaborating with equipment and material suppliers to develop new advanced chip packaging technology. This technology uses a rectangular substrate for packaging, replacing the current traditional circular wafer, to accommodate more chipsets on a single wafer. The report further mentioned that TSMC’s research is still in its early stages and might take several years to commercialize, but it represents a significant technological shift.

Reportedly, TSMC previously considered the challenge of using rectangular substrates to be too high, requiring substantial time and effort from both the company and its suppliers, along with upgrades or replacements of many production tools and materials.

Nikkei  also mentioned that TSMC is currently experimenting with rectangular substrates measuring 515 mm in length and 510 mm in width, providing more than three times the usable area of a 12-inch wafer.

TSMC is expanding its advanced chip packaging capacity, with the expansion of the Taichung plant mainly for NVIDIA, while the Tainan plant is primarily for Amazon and its chip design partner Alchip Technologies.

TSMC’s CoWoS advanced chip packaging can combine two sets of NVIDIA Blackwell GPU chips and eight sets of high-bandwidth memory (HBM). As single chips need to accommodate more transistors and integrate more memory, the mainstream 12-inch wafer might not be sufficient for packaging advanced chips in two years.

Samsung and Intel have also recognized the aforementioned issues and are investing in next-generation advanced packaging technologies.

Samsung currently offers advanced packaging services such as I-Cube 2.5D packaging, X-Cube 3D IC packaging, and 2D FOPKG packaging. For applications requiring low-power memory integration, such as mobile phones or wearable devices, Samsung already provides platforms like fan-out panel-level packaging and fan-out wafer-level packaging.

Intel is planning to launch the industry’s first glass substrate solution for next-generation advanced packaging, with mass production scheduled between 2026 and 2030. Intel anticipates that data centers, AI, and graphics processing—markets that require larger volume packaging and higher-speed applications and workloads—will be the first to adopt this technology.

Read more

• [News] TSMC Reportedly Develops Panel-Level Packaging, Another New Chip Packaging Tech
• [News] Samsung Reportedly Targets Q4 Trial Production of SiP Glass Substrate, Competing with Intel in the Advanced Packaging Market

(Photo credit: Intel)

According to Chinese media ChinaFund, there are reports that TSMC is increasing prices for its advanced 3nm and 5nm process nodes and advanced packaging. The report also cites a Morgan Stanley Securities prediction that Hua Hong Semiconductor may raise prices by 10% in the second half of the year.

Notably, China’s wafer foundries are showing signs of reducing domestic competition. While foundry price increases are not yet confirmed, utilization rates at major foundries have significantly improved, with many operating at full capacity or even exceeding 100%.

Industry sources cited by ChinaFund believe that the sustained increase in utilization rates and full capacity at some foundries could lead to potential price hikes in the future.

TSMC was the first to signal a price hike in the wafer foundry sector. Reports indicate that the global leader in foundry will increase prices for its advanced 3nm and 5nm nodes, with a potential 5% increase for 3nm and a 10%-20% rise for advanced packaging next year.

TSMC’s 5nm node continues to receive AI semiconductor orders, maintaining high capacity utilization.

At the same time, a recent Morgan Stanley report stated that Hua Hong Semiconductor, one of China’s leading foundries, is currently operating at over 100% capacity and may raise wafer prices by 10% in the second half of this year.

In an interview with ChinaFund, United Nova Technology CEO Michael Zhao stated that the semiconductor industry’s basic pattern of change starts with memory, then digital, and finally analog ICs. “Whether it’s a downturn or recovery, this is the sequence,” he emphasized.

“We are experiencing the same trend in the power semiconductor sector. We were at full capacity in Q4 last year and saw a significant recovery in Q1 this year.”

According to tracked data cited by ChinaFund, power semiconductor manufacturers have collectively raised prices this year. Sanliansheng increased prices by 10%-20%, Bluecolor by 10%-18%, Gaoge Microchip by 10%-20%, and Jiejie Microelectronics raised prices for its Trench MOS by 5%-10%.

For the memory sector, TrendForce forecasts that Q2 DRAM contract prices will rise by 13%-18%, and NAND Flash contract prices by 15%-20%.

Huafu Securities projects that, given the gradual increase in foundry utilization rates and rising inventory levels in consumer electronics and other fields, end-market demand will clearly drive growth across the semiconductor supply chain.

ChinaFund reports that several chip companies have recently announced price increases, with some as high as 20%. For instance, Yaxin Microelectronics, Chiplink, and iCM have all issued price hike notices.

(Photo credit: SMIC)

Taiwan’s semiconductor giant, TSMC, faces overwhelming demand for its 3nm technology, with major clients like Apple and NVIDIA fully allocate its production capacity.

According to a report from Commercial Times, orders are expected to be filled through 2026. Reportedly, TSMC is planning to raise its 3nm prices by over 5%, and advanced packaging prices are anticipated to increase by approximately 10% to 20% next year.

The members of TSMC’s 3nm family include N3, N3E, N3P, as well as N3X and N3A. As the existing N3 technology continues to be upgraded, N3E, which began mass production in the fourth quarter of last year, targets applications such as AI accelerators, high-end smartphones, and data centers.

N3P is scheduled for mass production in the second half of this year and is expected to become mainstream for applications in mobile devices, consumer products, base stations, and networking through 2026. N3X and N3A are customized for high-performance computing and automotive clients.

Source: TSMC

Per the industry sources cited by the same report, TSMC’s Zhunan advanced packaging plant (AP6), operational for a year now, has become Taiwan’s largest CoWoS base with the equipment moved into its AP6C plant. In the third quarter, CoWoS monthly production capacity is expected to double from 17,000 to 33,000 wafers.

Industry sources cited by the report further suggests that while AI accelerators do not use the most cutting-edge manufacturing processes, they rely heavily on advanced packaging technology. The ability of global semiconductor companies to secure more advanced packaging capacity from TSMC will determine their market penetration and control.

TSMC’s advanced packaging capacity is scarce, with primary customer NVIDIA having the highest demand, occupying about half of the capacity, followed closely by AMD. Broadcom, Amazon, and Marvell have also expressed strong interest in using advanced packaging processes. With gross margins close to 80%, NVIDIA is said to agree to price increases to secure more advanced packaging capacity, thereby distancing itself from competitors.

Previously, NVIDIA CEO Jensen Huang emphasized that TSMC is not just manufacturing wafers but also handling numerous supply chain issues. He also agreed that the current pricing is too low and would support TSMC’s price increase actions.

The industry sources cited by Commercial Times have indicated that TSMC plans to add CoWoS-related equipment by the third quarter and has requested equipment manufacturers to dispatch more engineers to fully staff its Longtan AP3, Zhunan AP6, and Central Taiwan Science Park AP5 plants.

In addition to Zhunan’s AP6C, the Central Taiwan Science Park plant, which originally only handled the latter stages of oS, will also gradually transition to CoW processes. Meanwhile, the Chiayi site is in the land preparation stage and is expected to progress faster than Tongluo.

Reportedly, industry sources further reveal that the prices for advanced process nodes such as 3nm and 5nm will also be adjusted. Particularly, strong demand for 3nm orders in the second half of the year is expected to drive utilization rates to near full capacity, extending through 2025. The 5nm process is experiencing similar demand dynamics, driven by AI needs.

Read more

• [News] Major Clients Reportedly Fully Allocate TSMC’s Production Capacity Until 2026, 3nm Process in High Demand
• [News] NVIDIA CEO Jensen Huang Supports C.C. Wei’s Theory and Backs for TSMC to Increase Price

(Photo credit: TSMC)

Vanguard International Semiconductor (VIS), an affiliate of TSMC, announced today a joint venture with NXP to build a 12-inch fab in Singapore. According to its press release, the construction is set to begin in the second half of 2024, with mass production expected by 2027. The initial investment for the fab is approximately USD 7.8 billion.

VIS stated in the official press release that it will establish a joint venture company, VisionPower Semiconductor Manufacturing Company (VSMC), with NXP in Singapore to build a 12-inch fab. The joint-venture fab will support 130nm to 40nm mixed-signal, power management and analog products, targeting the automotive, industrial, consumer and mobile end markets, of which its underlying process technologies are planned to be licensed and transferred to the joint venture from TSMC.

The company further stated that the joint venture will begin construction of the initial phase of the wafer fab in the second half of 2024, pending receipt of all required regulatory approvals, with initial production available to customers during 2027.

The joint venture will operate as an independent, commercial foundry supplier, providing assured proportional capacity to both equity partners, with an expected output of 55,000 300mm wafers per month in 2029. The joint venture will create approximately 1,500 jobs in Singapore. Upon the successful ramp of the initial phase, a second phase will be considered and developed pending commitments by both equity partners.

The total cost of the initial build out is anticipated to be USD 7.8 billion. VIS will inject USD 2.4 billion representing a 60 percent equity position in the joint venture and NXP will inject $1.6 billion for the remaining 40 percent equity position. VIS and NXP have agreed to contribute an additional USD 1.9 billion which will be utilized to support the long-term capacity infrastructure. The remaining funding including loans will be provided by third parties to the joint venture. The fab will be operated by VIS.

“VIS is pleased to work with leading global semiconductor company NXP to build our first 300mm fab. This project aligns with our long-term development strategies, demonstrating VIS’ commitment to meeting customer demands, and diversifying our manufacturing capabilities,” said VIS Chairman Leuh Fang.

“NXP continues to take proactive actions to ensure it has a manufacturing base which provides competitive cost, supply control, and geographic resilience to support our long-term growth objectives,” said Kurt Sievers, NXP President and CEO. “We believe VIS is well suited and fully understands the complexities involved in building and operating together with NXP a 300mm analog mixed signal fab. The joint venture partnership we intend to create with VIS perfectly aligns within NXP’s hybrid manufacturing strategy.”

Regarding this move, TrendForce posits that it reflects the trend of global supply chains shifting “Out of China, Out of Taiwan”(OOC/OOT), with Taiwanese companies accelerating their overseas expansion to improve regional capacity flexibility and competitiveness.

TrendForce noted that the semiconductor supply chain has been diversifying over the past two years to mitigate geopolitical and pandemic-related risks, forming two major segments: China’s domestic supply chain and a non-China supply chain. Recent US tariff increases have accelerated this shift, leading to increased orders from American customers.

Consequently, Vanguard’s capacity utilization rate is expected to rise to approximately 75% in the second half of this year, exceeding initial expectations. Additionally, inquiries for capacity at Vanguard’s existing Singapore Fab 3E plant have significantly increased, indicating potential support for the new plant’s capacity from customer demand and order transfers, according to Trendforce.

Read more

• Taiwanese Chipmakers Expand Overseas to Capitalize on Geopolitical Shifts and De-Sinicization Benefits, Says TrendForce
• [COMPUTEX 2024] The Rise of Generative AI Sparks Innovation across Industries, with Taiwan-based Companies Leading as Essential Partners in the Global Supply Chain

(Photo credit: VIS)