At TSMC’s 2024 Technology Symposium in late May, Kevin Zhang, TSMC Senior Vice President of Business Development, has shared the company’s latest development on advanced packaging. This article recaps the highlights in the forum, featuring TSMC’s breakthroughs regarding advanced packaging.

Advanced Packaging

SoW (System-on-Wafer Integration Technology)

SoW adopts TSMC’s InFO and CoWoS packaging technologies to integrate logic dies and HBM memory on the wafer. By doing so, TSMC aims to enhance performance and speed not just at the chip level, but the system level as well.

Currently, TSMC’s system-on-wafer manufactured with InFO technology has entered mass production. Afterwards, the company plans to develop and launch SOW using CoWoS technology to integrate SoC or SoIC, HBM, and other components together.

TSMC eyes its System-on-Wafer manufactured with the CoWoS technology to enter mass production in 2027, while its target applications would include AI and HPC, expanding the computational power needed for data centers of the next generation.

3DFabric

TSMC’s 3DFabric technology family includes three major platforms: SoIC, CoWoS, and InFO, encompassing both 2D and 3D front-end and back-end interconnect technologies.

SoIC

The SoIC platform offers two stacking solutions: SoIC-P (Bumped) and SoIC-X (Bumpless). The first solution, SoIC-P, is a micro-bump stacking solution suitable for cost-effective applications such as mobile devices.

The other solution, SoIC-X, adopts Hybrid Bonding, which is ideal for HPC and AI demands. The advantage of this solution is that the pitch between contacts can be reduced to a few micrometers (µm), increasing the interconnect interface between two chips while achieving a new level of interconnect density.

TSMC’s current bond pitch density with Hybrid Bonding has been reduced to 6 micrometers, and it aims to further reduce it 2 to 3 micrometers. In the meantime, the company has been advancing micro-bump technology, currently at over 30 micrometers, with the future goal of reducing it to the teens.

TSMC revealed that customer demand for SoIC-X technology has been increasing, with 30 customer design tape-outs expected by the end of 2026.

CoWoS / InFO

The CoWoS advanced packaging family includes three members: CoWoS-S, CoWoS-L, and CoWoS-R. The three platforms can mainly be differentiated by their intermediate layer materials, which may also affect the cost. In other words, CoWoS-S utilizes silicon interposer, CoWoS-L uses LSI (Local Silicon Interconnect), while CoWoS-R uses RDL (Redistribution Layer) wiring to connect small chips.

Depending on product requirements, SoIC chips can be integrated with either CoWoS or InFO. AMD’s MI300A / MI300 X is the first product to adopt SoIC-X and CoWoS technology.

One of the most well-known product which adopts TSMC’s CoWoS-L technology would be NVIDIA’s Blackwell AI accelerator, which integrates two SoCs using 5nm with eight HBM into one module.

Moreover, TSMC’s CoWoS technology integrates advanced SoCs/SoICs with HBM to meet the requirements of AI chips. Its SoIC has entered mass production through the CoWoS-S platform. Going forward, TSMC plans to develop a SoIC chip with an eight-time mask size (using the A16 process) and a CoWoS solution with 12 HBM stacks. This updated version is expected to enter mass production in 2027.

(Photo credit: TSMC)

On May 30th, Taiwanese Minister of Ministry of Economic Affairs, J.W. Kuo, proposed a crucial industry policy. According to a report from China Times, the first step is to take Taiwan’s manufacturing parks global, with the initial site planned for Kyushu, in conjunction with TSMC’s Kumamoto fab, to create a semiconductor industrial park.

Additionally, the ministry reportedly plans to invite the world’s top 100 companies to set up sales offices in Taiwan as well as offering tax incentives, to attract around 400 million consumers from Japan, South Korea, the Philippines, Vietnam, and other regions.

Kuo further emphasized the importance of the government’s proactive stance on taking small and medium-sized enterprises (SMEs) and their supply chains overseas. The Ministry of Economic Affairs is said to be planning to utilize state-owned enterprises or establish a development service company to help eliminate obstacles to overseas investment. Meanwhile, it also plans to establish an overseas one-stop service window to expedite the setup of plants by companies.

He then pointed out that TSMC already has two fabs in Kumamoto, Japan. The plan, as per the same report, is to set up a semiconductor industrial park in Kyushu, bringing Taiwan’s supply chain to Japan. This park will not only serve TSMC but also local Japanese companies.

Looking ahead, the industrial parks will primarily follow TSMC, expanding to Japan, the USA, and Germany, with plans to relocate 10 to 15% of the supply chain capacity.

Kuo expressed the vision of considering Japan, South Korea, the Philippines, and Vietnam, all within a three-hour flight radius, as Taiwan’s domestic market. Additionally, within four years, the goal is to attract 500 Michelin-starred restaurants, along with popular performances and medical beauty services, to draw consumers from neighboring Asian countries to Taiwan.

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(Photo credit: TSMC)

According to a report from Liberty Times, Taiwanese foundry UMC stated yesterday that the company’s operations in the second quarter would see a slight increase compared to the first quarter, and the second half of the year would be better than the first half.

With UMC’s technology and processes, the company estimated that it can capture about 10-20% of the AI foundry market share, which is expected to drive future business growth.

• Edge Computing to Become Widespread in 4 Years

At UMC’s shareholder meeting yesterday, Co-General Manager Jason Wang stated that semiconductor applications are becoming increasingly diverse and important. The most promising growth areas include autonomous vehicles, AI servers, and AI PCs.

UMC sees significant growth potential in high-speed transmission and power management. In high-performance computing (HPC), UMC will focus on back-end integration, including interposers and advanced 3D IC packaging.

Jason Wang pointed out that AI is currently in early stages, and thus more focused on building the infrastructure for high-speed computing. However, once the infrastructure is complete, the market will gradually expand to the widespread adoption of edge computing, which he estimates will take about four years.

UMC plans to position itself early, developing technologies that align with customer applications. UMC is optimistic about the market prospects and has high expectations for the future, Wang noted.

UMC’s CFO Chitung Liu stated that while UMC does not have advanced processes for producing HPC chips in the AI field, it has made significant progress in edge computing and related process technologies. With UMC’s technology, processes, and capacity, it is estimated that the company can still capture a 10-20% share of the AI foundry market, which is considerable and will be a major driver of future operational growth.

UMC currently produces CoWoS advanced packaging-related silicon interposers at its Singapore plant, with monthly capacity doubling to 6,000 wafers this year. UMC will continue to invest according to market conditions, according to Liu.

• Effects of U.S.-China Trade War Order Transferring Take At Least Six Month to be Seen

Regarding the benefits of diversification amid the U.S.-China trade war, Liu mentioned that it takes time for customers to redesign and transition orders. It can take at least six to nine months in the short term for the effects to be seen, and up to one to two years in the long term for orders to be successfully transitioned.

Currently, there are no significant effects from diversification in the short term. However, UMC’s production is diversified across regions including Singapore, Japan, China, and Taiwan, with collaborations with Intel in Arizona, USA. Thus, UMC can meet customer needs regardless of where they choose to manufacture, Liu explained.

Liu reiterated the stance from last month’s briefing, stating that the situation in the first half of the year has improved from the economic downturn, and second-quarter revenue is expected to see a slight increase compared to the previous quarter. He hopes for better performance in the second half of the year.

In terms of application markets, the short-term performance of the automotive and industrial sectors appears weak, but growth is expected in the medium to long term. On the other hand, prospects for the communication and consumer sectors in the second half of the year are expected to be better than the first half.

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(Photo credit: UMC)

Sales of semiconductor manufacturing equipment in Japan have been reportedly strong, with April 2024 witnessing the largest increase in sales in 17 months, continuing to surpass the JPY 300 billion mark and setting a new record for the highest monthly sales. The sales volume for the period from January to April also reached a historical high for the same period.

The Semiconductor Equipment Association of Japan (SEAJ) announced on May 27th that the sales of Japanese-made semiconductor equipment in April 2024 (three-month moving average, including exports) reached JPY 389.106 billion, an increase of 15.7% compared to the same month last year. This marks the fourth consecutive month of growth, showing the largest increase in 17 months (since November 2022), with a remarkable growth rate of 19.1%.

Monthly sales have exceeded JPY 300 billion for the sixth consecutive month, surpassing the previous record of JPY 380.929 billion in September 2022, setting a new historical high for single-month sales.

Compared to the previous month (March 2024), sales grew by 6.4%, marking the sixth consecutive month of month-on-month growth.

The cumulative sales of Japanese semiconductor equipment from January to April 2024 reached JPY 1.387079 trillion, a 9.4% increase compared to the same period last year, setting a new historical high for this period.

Japan’s global market share of semiconductor equipment (calculated based on sales) stands at 30%, making it the second-largest in the world, following the United States.

In a financial report press release on May 10, Japanese chip equipment giant Tokyo Electron (TEL) indicated that the increased demand for DDR5 and HBM from the second half of this year is expected to drive a recovery in investment in the leading-edge DRAM.

As a result, the global market size for front-end chip manufacturing equipment (Wafer Fab Equipment; WFE) in 2024 is projected to grow by 5% year-on-year to approximately 100 billion USD, matching the current historical high recorded in 2022 (around USD 100 billion). Additionally, with continued growth in AI servers and a recovery in demand for PCs and smartphones, the WFE market is anticipated to see a double-digit increase (over 10%) in 2025 compared to 2024.

In a financial report press release on May 9, semiconductor equipment company Screen Holdings stated that due to investments in mature processes in China and investments in the most advanced processes in Taiwan, the WFE market is expected to grow in 2024, with an estimated annual increase of about 5%.

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(Photo credit: TEL)

According to a report from TechNews, TSMC held a technology forum on May 23, where Senior Fab Director pointed out that benefiting from HPC and mobile phone demands, the 3nm production capacity this year has more than tripled compared to last year, but this is actually still not enough, so efforts are still being made to meet customer demand.

During the forum, TSMC also indicated that its compound annual growth rate (CAGR) in advanced processes below 7nm surpassed 25% from 2020 to 2024. Moreover, TSMC remains committed to investment, with capital expenditure in 2024 increasing by 10% compared to the preceding four years.

Due to the booming demand for AI and HPC, TSMC is actively expanding its capacity for advanced processes. Huang stated that TSMC’s capacity for SoIC and CoWoS is experiencing CAGRs exceeding 100% and 60%, respectively, from 2022 to 2026.

The topic of TSMC’s manufacturing has always been a focus of the industry. In the past, it was presented by Executive Vice President and Co-Chief Operating Officer Y.P. Chyn, Vice President of Fab Operations I Dr. Y.L. Wang, and TSMC Vice President of Advanced Technology and Mask Engineering Dr. T.S. Chang. This time, it is presented for the first time by the key driver of the most advanced process and plant-level executives in Taiwan.

He mentioned that the share of TSMC’s special processes in maturity has also steadily increased, from 61% in 2020 to the target of 67% in 2024.

Huang further pointed out that TSMC averaged the construction of five fabs per year  between 2022 and 2023, increasing to seven this year. Among them are three fabs, two packaging plants, and two overseas facilities.

Fab 20 in Hsinchu and Fab 22 in Kaohsiung are both 2nm fabs, progressing smoothly and expected to commence production next year.

Taichung AP5 is expanding its capacity to meet the needs for CoWoS production, while the recently announced advanced packaging investment in Chiayi is for CoWoS and SOIC production.

In terms of global deployment, three fabs are planned in Arizona, USA. The first fab is already had its first tool-in, set to commence 4nm production next year, while the second fab is scheduled for 2028 production, and the third fab is expected to begin production by the end of the 2020s. In Japan, Kumamoto Fab 1 is slated for production in the fourth quarter of this year, with Fab 2 set for production in 2027.

In Europe, the Dresden fab will offer 16nm technology, with construction beginning in the fourth quarter of this year and production slated for 2027, mainly to meet European customer needs. Additionally, Nanjing Fab 16 in China continues to expand its 28nm capacity.

When discussing the application of EUV technology, he mentioned that TSMC’s EUV machine count has grown tenfold since 2019, now accounting for 65% of the global total. Both wafer output and efficiency have significantly increased along with learning.

Read more

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(Photo credit: TSMC)