According to a report from CNA, the South Korean government has announced a comprehensive support plan for the semiconductor industry, amounting to KRW 26 trillion (roughly USD 19 billion). The plan includes substantial financial support, expansion of semiconductor parks, infrastructure development, and investment in R&D and talent cultivation, aimed at revitalizing the economy and improving livelihoods.

Reportedly, South Korean President Yoon Suk Yeol chaired the second economic review meeting, where this semiconductor industry support plan was unveiled. The centerpiece of the plan is a KRW 17 trillion financial support program provided by the Industrial Bank of Korea, designed to alleviate potential funding challenges that companies may face when constructing new factories, production lines, and equipment.

The tax reduction incentives, originally set to expire this year, is said to be extended, allowing semiconductor companies to partially offset their R&D and equipment investment costs against income taxes. Yoon stated that the Tax reduction incentives encourage companies to expand their investments, benefiting not only the companies themselves but also creating more quality job opportunities.

He emphasized that over 70% of the support will be directed towards small and medium-sized enterprises (SMEs), rather than just large corporations. Yoon further expressed that as the economy grows, tax cuts will actually generate more tax revenue.

Additionally, a KRW 1 trillion semiconductor ecosystem fund will be established to support smaller semiconductor SMEs with specialized technologies in wafer design, materials, components, and equipment, helping them to become world-class enterprises.

President Yoon also instructed to expedite the construction of semiconductor mega-parks and pledged cooperation with various government agencies to accelerate the resolution of infrastructure needs such as electricity, water, and external roads for the industry.

Particularly concerning the critical issue of power supply affecting yield rates, the government will intensify communication with the parliament to expedite the passage of a special law regarding grid use, which can significantly shorten the construction time for power transmission lines.

Investments in infrastructure are expected to exceed KRW 2.5 trillion, with the construction time for industrial parks projected to be reduced from 7 years to 3.5 years. Additionally, there is a plan to allocate KRW 5 trillion for manpower development from 2025 to 2027, a significant increase from the KRW 3 trillion allocated from 2022 to 2024.

President Yoon pointed out that the future success of the semiconductor industry hinges on system semiconductors, which account for two-thirds of the overall market.

Therefore, the government must collaborate with businesses to propose groundbreaking initiatives to enhance the competitiveness of system semiconductors, ensuring a dominant position in the international market. This comprehensive support plan is expected to be formally implemented shortly after finalization, potentially as early as mid-June.

As per a report from the Korean media outlet TheElec, a semiconductor fund initially planned at 300 billion won has been expanded to KRW 1.1 trillion. The original 7-year construction plan for the semiconductor cluster will be halved, according to South Korea’s Deputy Prime Minister Choi Sang-mok.

The remaining portion of the KRW 26 trillion investment will reportedly be dedicated to fostering researchers in the semiconductor field. South Korean chipmakers Samsung and SK Hynix welcomed the announcement, emphasizing the need for ongoing government support.

Read more

• [News] South Korea Reportedly Plans to open AI Chip Center in San Jose
• [News] South Korea Reportedly Pushes for KRW 10 Trillion Investment Plan to Strengthen Semiconductor Industry Position

(Photo credit: Samsung)

TSMC’s Nanjing plant has averted an export permit expiration crisis. On May 23rd, TSMC confirmed that it has recently received the “Validated End-User” (VEU) authorization from the U.S. Department of Commerce for TSMC (Nanjing) Co., Ltd., according to a report by Commercial Times.

Currently, the same report noted that the Nanjing plant focuses on mature processes such as 16nm and 28nm, and will continue to expand to meet customer demand. With the official U.S. authorization, the plant will no longer require individual case reviews.

TSMC stated that this formal VEU authorization replaces the temporary written authorization issued by the Department of Commerce since October 2022. The VEU does not grant new privileges but confirms that the items and services covered under U.S. export control regulations can continue to be supplied to TSMC (Nanjing) Co., Ltd. without the need for individual licenses from suppliers.

The VEU authorization allows TSMC’s Nanjing plant to maintain its current production status. Industry sources cited by Commercial Times noted that, although TSMC received its indefinite exemption later than Samsung, it has not affected TSMC’s competitiveness in the local market. Offering more competitive specialized processes is the key to TSMC’s continued customer trust.

Industry sources cited in the same report further pointed out that more specialized processes help TSMC tackle geopolitical risk challenges. For example, in the panel driver IC sector, after beginning mass production of 28nm high-voltage products this year, TSMC is now developing a 16nm high-voltage FinFET process to enable customers to design more competitive OLED panel driver ICs.

Additionally, TSMC is reportedly collaborating with customers to validate its 16nm consumer-grade products and co-develop automotive-grade 16nm magnetic random-access memory (MRAM) technology. TSMC is also progressing towards higher storage density and lower cost solutions in preparation for the next generation of 16nm MRAM.

TSMC is also accelerating its deployment of future technology applications such as software-defined vehicles (SDVs), smart sensors, and edge AI, developing the most suitable products for various regional markets, spanning from China, United States, Japan, and Germany.

Read more

• [News] TSMC’s Nanjing Plant Reportedly Pushes for Indefinite Exemption From US Before the May 31 Deadline
• [News] TSMC More Ambitious on CoWoS Capacity Expansion, Targeting 60% CAGR by 2026

(Photo credit: TSMC)

To alleviate the capacity constraints of CoWoS advanced packaging, NVIDIA is reportedly planning to accelerate the introduction of its GB200, into panel-level fan-out packaging. According to a report from Economic Daily News, originally scheduled for 2026, this shift has been moved up to 2025, sparking opportunities in the panel-level fan-out packaging sector.

Taiwanese companies like Powertech Technology Inc. (PTI) and AU Optronics (AUO) are said to have prepared with the necessary capabilities, expected to seize this market opportunity.

The sources cited by the report from Economic Daily News explain that fan-out packaging has two branches: wafer-level fan-out packaging (FOWLP) and panel-level fan-out packaging (FOPLP). Among Taiwanese packaging and testing companies, PTI is reportedly the fastest in deploying panel-level fan-out packaging.

To capture the high-end logic chip packaging market, PTI has fully dedicated its Hsinchu Plant 3 to panel-level fan-out packaging and TSV CIS (CMOS image sensors) technologies, emphasizing that fan-out packaging can achieve heterogeneous integration of ICs.

PTI previously expressed optimism about the opportunities presented by the era of panel-level fan-out packaging, noting that it can produce chip areas two to three times larger than wafer-level fan-out packaging.

Innolux, a major panel manufacturer, is also optimistic, forecasting that 2024 will be the advanced packaging mass production inaugural year for the group. The first phase capacity of its fan-out panel-level packaging (FOPLP) production line has already been fully booked, with mass production and shipments scheduled to begin in the third quarter of this year.

Chairman of Innolux Jim Hung emphasized that advanced packaging technology (PLP) connects chips through redistribution layers (RDL), meeting the requirements for high reliability, high power output, and high-quality packaging products. This technology has secured process and reliability certifications from top-tier customers, and its yield rates have been well received, with mass production set to commence this year.

Read more

• [News] No Demand Lull? NVIDIA Reportedly Points Out Hopper Will Remain in Short Supply for Some Time
• [News] NVIDIA’s H100 Chip Heat Declines, CoWoS Capacity Eases

(Photo credit: NVIDIA)

Samsung’s latest high bandwidth memory (HBM) chips have reportedly failed Nvidia’s tests, while the reasons were revealed for the first time. According to the latest report by Reuters, the failure was said to be due to issues with heat and power consumption.

Citing sources familiar with the matter, Reuters noted that Samsung’s HBM3 chips, as well as its next generation HBM3e chips, may be affected, which the company and its competitors, SK hynix and Micron, plan to launch later this year.

In response to the concerns raising by heat and power consumption regarding HBM chips, Samsung stated that its HBM testing proceeds as planned.

In an offical statement, Samsung noted that it is in the process of optimizing products through close collaboration with customers, with testing proceeding smoothly and as planned. The company said that HBM is a customized memory product, which requires optimization processes in tandem with customers’ needs.

According to Samsung, the tech giant is currently partnering closely with various companies to continuously test technology and performance, and to thoroughly verify the quality and performance of HBM.

Nvidia, on the other hand, declined to comment.

As Nvidia currently dominates the global GPU market with an 80% lion’s share for AI applications, meeting Nvidia’s stardards would doubtlessly be critical for HBM manufacturers.

Reuters reported that Samsung has been attempting to pass Nvidia’s tests for HBM3 and HBM3e since last year, while a test for Samsung’s 8-layer and 12-layer HBM3e chips was said to fail in April.

According to TrendForce’s analysis earlier, NVIDIA’s upcoming B100 or H200 models will incorporate advanced HBM3e, while the current HBM3 supply for NVIDIA’s H100 solution is primarily met by SK hynix. SK hynix has been providing HBM3 chips to Nvidia since 2022, Reuters noted.

According to a report from the Financial Times in May, SK hynix has successfully reduced the time needed for mass production of HBM3e chips by 50%, while close to achieving the target yield of 80%.

Another US memory giant, Micron, stated in February that its HBM3e consumes 30% less power than its competitors, meeting the demands of generative AI applications. Moreover, the company’s 24GB 8H HBM3e will be part of NVIDIA’s H200 Tensor Core GPUs, breaking the previous exclusivity of SK hynix as the sole supplier for the H100.

Considering major competitors’ progress on HBM3e, if Samsung fails to meet Nvidia’s requirements, the industry and investors may be more concerned on whether the Korean tech heavyweight would further fall behind its rivals in the HBM market.

(Photo credit: Samsung)

SK hynix has disclosed yield details regarding the company’s 5^th generation High Bandwidth Memory (HBM), HBM3e, for the first time. According to a report from the Financial Times, citing Kwon Jae-soon, the head of yield at SK hynix, the memory giant has successfully reduced the time needed for mass production of HBM3e chips by 50%, while close to achieving the target yield of 80%.

This is better than the industry’s previous speculation, which estimated the yield of SK Hynix’s HBM3e to be between 60% and 70%, according to a report by Business Korea.

According to TrendForce’s analysis earlier, NVIDIA’s upcoming B100 or H200 models will incorporate advanced HBM3e, while the current HBM3 supply for NVIDIA’s H100 solution is primarily met by SK hynix, leading to a supply shortfall in meeting burgeoning AI market demands.

The challenge, however, is the supply bottleneck caused by both CoWoS packaging constraints and the inherently long production cycle of HBM—extending the timeline from wafer initiation to the final product beyond two quarters.

The report by Business Korea noted that HBM manufacturing involves stacking multiple DRAMs vertically, which presents greater process complexity compared to standard DRAM. Specifically, the yield of the silicon via (TSV), a critical process of HBM3e, has been low, ranging from 40% to 60%, posing a significant challenge for improvement.

In terms of SK hynix’s future roadmap for HBM, CEO Kwak Noh-Jung announced on May 2nd that the company’s HBM capacity for 2024 and 2025 has almost been fully sold out. According to Business Korea, SK hynix commenced delivery of 8-layer HBM3e products in March and plans to supply 12-layer HBM3e products in the third quarter of this year. The 12-layer HBM4 (sixth-generation) is scheduled for next year, with the 16-layer version expected to enter production by 2026.

Read more

• [News] Samsung and SK Hynix Urgently Reallocate 20% of DRAM Production Capacity to Support Rising HBM demand
• [News] SK Hynix Accelerates HBM4E Development, Aiming for Mass Production by 2026

(Photo credit: SK hynix)