According to TrendForce’s latest memory spot price trend report. Details are as follows:

…

Amid the wave of AI applications, the demand for high-performance memory continues to mushroom, with DRAM, represented by HBM, gaining significant traction. Meanwhile, to further meet market demand, memory manufacturers are  poised to embrace a new round of DRAM technological “revolution.”

• 4F Square DRAM being Developed Smoothly

According to a report from Korean media outlet Chosun Biz, Samsung Electronics Vice President Changsik Yoo recently announced that Samsung’s next-generation DRAM technology is progressing well. In addition to the successful mass production of 1b DRAM, the development of 4F Square DRAM technology is also proceeding smoothly, with the initial sample of 4F Square DRAM set to be developed by 2025.

Industry sources cited by WeChat account DRAMeXchange indicate that the early DRAM cell structure was 8F Square, while currently commercialized DRAM mainly uses 6F Square. Compared to these two technologies, 4F Square employs a vertical channel transistor (VCT) structure, which can reduce the chip surface area by 30%.

As the cell area decreases, DRAM density and performance increase. Therefore, driven by applications like AI, 4F Square technology is gradually sought after by major storage manufacturers.

Previously, Samsung stated that many companies are working to transition their technology to 4F Square VCT DRAM, although some challenges need to be overcome, including the development of new materials like oxide channel materials and ferroelectrics.

Industry sources believe that the initial sample of Samsung’s 4F Square DRAM in 2025 might be for internal release. Another semiconductor manufacturer, Tokyo Electron, estimates that DRAM using VCT and 4F Square technology will come out between 2027 and 2028.

Furthermore, earlier media reports mentioned that Samsung plans to apply Hybrid Bonding technology to support the production of 4F Square DRAM. Hybrid Bonding is a next-generation packaging technology referring to vertically stack chips to increase cell density and thus improve performance, which will also exert an influence on the development of HBM4 and 3D DRAM.

• HBM4 on the Horizon

In the era of AI, HBM, particularly HBM3e, has thrived in the memory market, prompting fierce competition among the three major DRAM manufacturers. A new race is now underway, primarily focusing on the next-generation HBM4 technology.

In April of this year, SK Hynix announced a partnership with TSMC to jointly develop HBM4. It is reported that the two companies will first work on performance improvements for the base die fitted at the bottom layer within the HBM package. To focus on the development of next-generation HBM4 technology, Samsung has established a new “HBM Development Team.”

In July, Choi Jang-seok, head of the New Business Planning Group in Samsung Electronics’ memory division, revealed that the company is developing a high-capacity HBM4 memory with a single stack of up to 48GB, expected to go into production next year. Recently, Samsung reportedly plans to use a 4nm advanced process to produce HBM4 logic die. Micron, on the other hand, plans to introduce HBM4 between 2025 and 2027 and transition to HBM4E by 2028.

Aside from manufacturing processes, DRAM manufacturers are actively exploring hybrid bonding technology for future HBM products. Compared to existing bonding processes, hybrid bonding eliminates the need for bumps between DRAM memory layers, instead directly connecting the upper and lower layers, copper to copper. This significantly improves signal transmission speed, better matching the high bandwidth requirements of AI computing.

In April of this year, Korean media outlet The Elec reported that Samsung successfully manufactured a 16-layer stacked HBM3 memory based on hybrid bonding technology, with the memory sample functioning normally. This 16-layer stacked hybrid bonding technology will be used to produce HBM4 at scale in the future. SK Hynix plans to adopt hybrid bonding in its HBM production by 2026. Micron is also developing HBM4 and is considering related technologies, including hybrid bonding, which are all under research at present.

• The Development of 3D DRAM Picks up Steam

3D DRAM (Three-dimensional dynamic random-access memory) represents a new DRAM technology with a novel memory cell structure. Unlike traditional DRAM, which places memory cells horizontally, 3D DRAM vertically stacks memory cells, greatly increasing storage capacity per unit area and improving efficiency. This makes it a key development for the next generation of DRAM.

In the memory market, 3D NAND Flash has already achieved commercial application, while 3D DRAM technology is still under research and development. However, as AI, big data, and other applications enjoy burgeoning growth, the demand for high-capacity, high-performance memory will surge, and 3D DRAM is expected to become a mainstream product in the memory market.

HBM technology has paved the way for the 3D evolution of DRAM, enabling DRAM to transition from traditional 2D to 3D. However, current HBM cannot be considered as true 3D DRAM technology. Samsung’s 4F Square VCT DRAM is closer to the concept of 3D DRAM, but it is not the only direction or goal for 3D DRAM. Memory manufacturers have more ideas and creativity in 3D DRAM.

Samsung plans to achieve the commercialization of 3D DRAM by 2030. In 2024, Samsung showcased two 3D DRAM technologies, including VCT and stacked DRAM. Samsung first introduced VCT technology, then upgraded to stacked DRAM by stacking multiple VCTs together to continuously improve DRAM capacity and performance.

Samsung states that stacked DRAM can fully utilize the Z-axis space, accommodating more memory cells in a smaller area, with a single chip capacity exceeding 100Gb. In May of this year, Samsung noted that it, along with other companies, successfully manufactured 16-layer 3D DRAM, but emphasized that it is not ready for mass production. 3D DRAM is expected to be produced using wafer-to-wafer hybrid bonding technology, and BSPDN (Backside Power Delivery Network) technology is also considered.

Regarding Micron, industry sources cited by DRAMeXchange reveal that Micron has filed for a 3D DRAM patent application different from Samsung’s, aiming to alter the shape of transistors and capacitors without placing cells.

BusinessKorea reported in June that SK Hynix achieved a manufacturing yield of 56.1% for its 5-layer stacked 3D DRAM. This means that out of around 1000 3D DRAMs produced on a single test wafer, about 561 viable devices were manufactured. The experimental 3D DRAM demonstrated characteristics similar to the currently used 2D DRAM, marking the first time SK Hynix disclosed specific numbers and features of its 3D DRAM development.

Besides, American company NEO Semiconductor is also engaging in the development of 3D DRAM. Last year, NEO Semiconductor announced the launch of the world’s first 3D DRAM prototype: 3D X-DRAM. This technology resembles 3D NAND Flash, namely increasing memory capacity by stacking layers, offering high yield, low cost, and remarkably high density.

NEO Semiconductor plans to launch the first generation of 3D X-DRAM in 2025, featuring a 230-layer stack and a core capacity of 128Gb, which is several times higher than the 16Gb capacity of 2D DRAM.

Read more

• [News] Korean Semiconductor Exports Hit a New High, with Memory Shipment up by 88.7%
• [News] Korean Advanced Packaging Industry’s Rise Delayed by TSMC and ASE Expansion

(Photo credit: SK Hynix)

Chinese tech giant Huawei, which plans to launch its Mate 70 Series in the fourth quarter, is reportedly to feature the latest Kirin 9100 processor in these models. Though there were rumors indicating that the chip will be manufactured with SMIC’s 5nm node, according to a report by Wccftech, the next Kirin SoC for the Mate 70 Series will still be limited to SMIC’s 7nm process.

Kirin 9100’s predecessors, the Kirin 9000S and the Kirin 9010, have been mass-produced using SMIC’s 7nm (N+2) technology, the report notes. As market speculations previously indicated that Huawei might use 5nm in its next Kirin SoC, there seems to be a twist in Huawei’s plans.

According to Wccftech, the next Kirin SoC for the Mate 70 series will likely be mass-produced using SMIC’s N+3 process, which offers higher density compared to the N+2 variant. The move means that instead of transitioning to SMIC’s 5nm, Huawei’s latest Kirin SoC may choose to stay with 7nm.

It is worth noting that even under the U.S. export control, SMIC is said to successfully produce 5nm chips using DUV lithography instead of EUV, which is typically required for 5nm production. However, as the high cost and low yield of DUV make it a challenging feat for most manufacturers, Huawei’s decision may be practical.

As previously reported by the Financial Times, industry sources have indicated that SMIC’s prices for 5nm and 7nm processes are 40% to 50% higher than TSMC’s, while the yield less than one-third of TSMC’s. Later, it was estimated that SMIC’s 5nm chip prices would be up to 50 percent more expensive than TSMC’s on the same lithography, meaning that Huawei would face a tough time selling its Mate 70 series to consumers with a decent margin if it attempts to absorb a majority of those component costs.

Therefore, Wccftech now states that the Kirin 9100 might be fabricated using the 7nm process. By employing the N+3 node, it could achieve a higher density than the Kirin 9010 and the Kirin 9000S, which are manufactured by the N+2 node. This improvement means that the Kirin 9100 will have a higher transistor count, leading to better performance per watt and improved power efficiency.

Alongside the new chipset for the Mate 70 family, Huawei is rumored to be testing the same N+3 technology for its ARM-based hardware, the report notes.

Read more

• [News] Huawei Reportedly to Launch Kirin 9100 with Superior Performance to Snapdragon 8 Gen 2
• [News] SMIC Reportedly to Manufacture 5nm Chips for Huawei Without EUV Machinery

(Photo credit: Hisilison)

According to a report from Nikkei on July 23rd, since 2021, the establishment of TSMC’s plants has potentially spurred over 100 semiconductor-related investment projects in Kyushu, known as Japan’s “Silicon Island.”

The disclosed investment amount by companies alone reaches JPY 4.74 trillion, and when including undisclosed investments, it is estimated to reach JPY 5 trillion. TSMC’s establishment in Kumamoto Prefecture has attracted investments from local material, logistics, and other companies.

Kyushu is a major hub for Japan’s semiconductor industry and is often referred to as “Silicon Island,” mirroring the name of Silicon Valley in the United States.

Reportedly, according to data compiled by the Kyushu Bureau of Economy, Trade, and Industry, there have been 100 semiconductor-related investment projects in Kyushu from April 2021 to June 2024, with 72 of these projects disclosing their investment amounts. Kumamoto Prefecture leads with 52 projects, followed by Fukuoka Prefecture with 15 projects. TSMC’s Kumamoto plants (Plant 1 and Plant 2) account for over 60% of the total investment amount.

The combined investment in TSMC’s Kumamoto Plant 1 and Plant 2 exceeds USD 20 billion, with the Japanese government providing up to JPY 1.2 trillion (roughly USD 7.7 billion) in subsidies for these two plants.

In addition, Sony began constructing a new image sensor plant in Koshi, Kumamoto Prefecture, in April. Rohm plans to invest JPY 300 billion in a new plant in Kunitomi, Miyazaki Prefecture, to produce power semiconductors and other products. SUMCO, a major silicon wafer manufacturer, will invest over JPY 400 billion in Kyushu to expand existing plant capacity and build a new factory in Yoshinogari, Saga Prefecture.

The report further highlights that future attention will be focused on whether Taiwanese companies with existing business relationships with TSMC will follow suit and invest in Kyushu.

TSMC’s plant in Kikuyo, Kumamoto Prefecture (Kumamoto Plant 1), is expected to begin mass production in Q4 (October-December) of this year, utilizing 28/22nm and 16/12nm process technologies with a monthly production capacity of 55,000 wafers. Kumamoto Plant 2 is scheduled to start construction at the end of 2024 and begin operations by the end of 2027, focusing on 6/7nm technology. The combined monthly production capacity of Kumamoto Plant 1 and Plant 2 is estimated to exceed 100,000 wafers.

Read more

• [News] TSMC’s Kumamoto Fab 2 Reportedly Begins Land Preparation
• [News] Kumamoto Vying for TSMC’s Third Fab, Looking to Build Semiconductor Hub

(Photo credit: TSMC)

As TSMC stands at the core of the global semiconductor industry, NVIDIA founder Jensen Huang stirred up an AI frenzy when he visited Taiwan in June. According to a report from Commercial Times, during his visit, he met with TSMC founder Morris Chang and then-President C.C. Wei, and personally visited TSMC’s headquarters.

According to a report by Mirror Media on July 23rd, sources revealed that Huang requested TSMC to set up a dedicated CoWoS production line for NVIDIA at an external facility. However, this request was met with skepticism from TSMC’s senior management, resulting in a tense situation.

Notably, TSMC Chairman C.C. Wei recently pointed out that despite strong AI demand, the company has yet to achieve a supply-demand balance and continues to increase production capacity. Many customers are eager for advanced process capacity, and TSMC is striving to balance pricing and capacity. Wei also revealed that the profit margins for advanced packaging CoWoS are being adjusted to align more closely with the company’s average profit levels.

C.C. Wei emphasized TSMC’s commitment to meeting customer demands with three “Whatever” statements. Regarding timelines, he revealed that supply will remain tight through 2025, with hopes for improvement by 2026.

Sources cited by the report further estimates that current utilization rates for 5nm and 3nm processes are at full capacity. To address demand, production for 3nm is set to increase gradually from 100,000 wafers per month to approximately 125,000 wafers per month by the second half of the year.

The 2nm process is expected to start mass production in the fourth quarter of 2025, with a target monthly output of 30,000 wafers. With future expansion at the Kaohsiung plant, the combined monthly capacity of the Hsinchu Science Park and Kaohsiung facilities is projected to reach 120,000 to 130,000 wafers.

Despite escalating geopolitical risks, Wei stated that there will be no changes to TSMC’s expansion strategy, with projects in Arizona, Japan’s Kumamoto, and future European facilities proceeding as planned.

Currently, TSMC’s investment in its U.S. facilities has reached USD 65 billion. The Arizona site is expected to have three plants, with the first two set to start production in 2025 and 2028, focusing on 4/3nm and 3/2nm nodes, respectively.

TSMC’s advanced packaging plans in Taiwan include facilities in Hsinchu Science Park, Miaoli Zhunan, Taichung Central Taiwan Science Park, Tainan Southern Taiwan Science Park (taking over Longtan InFO), and Taoyuan Longtan (significantly expanding CoWoS). Construction is also scheduled to begin in 2024 at Miaoli Tongluo and Chiayi Science Park.

Read more

• [News] Decipher TSMC in Key Figures: Some Facts Needed to be Known
• [News] TSMC Reportedly Sees Strong 4nm Demand, with NVIDIA’s Order Up by 25%

(Photo credit: TSMC)