In early June, NVIDIA CEO Jensen Huang revealed that Samsung’s High Bandwidth Memory (HBM) is still striving on the certification process, but is one step away from beginning supply. On July 4^th, a report from Korea media outlet Newdaily indicated that Samsung has finally obtained approval from the GPU giant for qualification of its 5th generation HBM, HBM3e. It is expected that Samsung will soon proceed with the subsequent procedures to officially start mass production for HBM supply, the report noted.

Citing sources from the semiconductor industry, the report stated that Samsung recently received the HBM3e quality test PRA (Product Readiness Approval) notification from NVIDIA. It is expected that negotiations for supply will commence afterward.

However, just one hour after the news reported that Samsung’s HBM3e passed NVIDIA’s tests, another media outlet, Hankyung, noted that Samsung has denied the rumor, clarifying it is “not true,” and that the company is consistently undergoing quality assessments.

TrendForce reports that Samsung is still collaborating with NVIDIA and other major customers on the qualifications for both 8-hi and 12-hi HBM3e products. The successful qualification mentioned in the article was only an internal achievement for Samsung. Samsung anticipates that its HBM3e qualification will be partially completed by the end of 3Q24.

Per a previous report from Reuters, Samsung has been attempting to pass NVIDIA’s tests for HBM3 and HBM3e since last year, while a test for Samsung’s 8-layer and 12-layer HBM3e chips was said to fail in April.

According to the latest report from Newdaily, Samsung’s breakthrough came about a month after the memory heavyweight sent executives in charge of HBM and memory development to the U.S. at NVIDIA’s request. Previously, it was reported that Samsung had failed to pass the quality test as scheduled due to issues such as overheating.

The report further stated that though from Samsung’s perspective, supplying HBM to NVIDIA was crucial, NVIDIA is also eager to receive more HBM, with the overwhelming demand for AI semiconductors and the impending mass production of its next-generation GPU Rubin, which significantly increases HBM usage.

According to the report, Samsung is expected to eliminate uncertainties in HBM and start full-scale mass production, giving a significant boost to its memory business. There are also suggestions that its HBM performance could see a quantum leap starting in the second half of the year.

On the other hand, Samsung’s major rival, SK hynix, is the primary supplier of NVIDIA’s HBM3 and HBM3e. According to an earlier TrendForce’s analysis, NVIDIA’s upcoming B100 or H200 models will incorporate advanced HBM3e, while the current HBM3 supply for NVIDIA’s H100 solution is primarily met by SK hynix.

According to a report from the Financial Times in May, SK hynix has successfully reduced the time needed for mass production of HBM3e chips by 50%, while close to achieving the target yield of 80%.

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• [News] Jensen Huang Confirms NVIDIA Approaches Certification of Samsung’s HBM Chips
• HBM3e Production Surge Expected to Make Up 35% of Advanced Process Wafer Input by End of 2024, Says TrendForce

(Photo credit: Samsung)

MediaTek and Xiaomi Group have deepened their collaboration. On July 2, Xiaomi China’s Vice President of Marketing and General Manager of the Redmi brand, Wang Teng, announced on Weibo that the joint laboratory between Xiaomi and MediaTek has officially opened at Xiaomi’s Shenzhen R&D Center, with the new “Redmi K70 Supreme Edition” being the first product from the joint lab.

According to a report by etnet, the joint laboratory between Xiaomi and MediaTek covers five core capabilities, focusing on three major technological parts: performance, communication, and AI.

MediaTek, a global leader in smartphone chip shipment, maintains close cooperation with its brand clients.

Wang noted that following the Post-Performance Era Launch event last year, the cooperation between Xiaomi and MediaTek has reached another notch with a  goal of creating the strongest product performance experience and realizing the pre-research and implementation of the latest technologies.

A report from ithome revealed that Xiaomi and MediaTek have already entered into several collaborative agreements in the past, in which Xiaomi was often the first to launch new Dimensity processors. The two companies have also co-developed several Ultra versions of Dimensity processors.

Wang described the K70 Supreme Edition as the “performance demon” and the most sincere value-for-money product, offering a more comprehensive flagship experience. It is a gold standard for Dimensity performance jointly created by Redmi and MediaTek, aiming for three number ones: highest performance scores, best game frame rate/energy efficiency, and longest concurrent operation of super frame rate and super resolution.

Wang also mentioned that especially for the third goal, MediaTek, based on Dimensity 9300+ chip, has equipped the K70 Supreme Edition with the new-generation gaming discrete GPU and its self-developed dual-chip scheduling technology. “Not only to achieve super frame rate and super resolution in original/iron mode but also to realize the longest concurrent operation time, allowing users to enjoy games for longer periods.”

MediaTek Dimensity 9300+ is part of the Dimensity 9300 series of chips, launched in May this year. It is built using TSMC’s 4nm process and features an eight-core CPU with four Cortex-X4 super cores, reaching a maximum frequency of 3.4GHz, surpassing the level of Dimensity 9300.

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• [News] China’s Xiaomi and Unisoc Claim Domestic 4nm Mobile Processors Coming Soon
  

(Photo credit: MediaTek)

China aims to establish at least 50 AI standards by 2026, as outlined in a new draft policy from Beijing, according to a report by South China Morning Post. The draft policy, released on Tuesday by the Ministry of Industry and Information Technology (MIIT), will not only cover training for large language models (LLMs), but even semiconductors.

This initiative is part of China’s effort to catch up with the U.S. in AI development, the report noted. Earlier in April, Alibaba’s chairman, Joe Tsai, mentioned in an interview that China is at least two years behind its leading US counterparts, like OpenAI and Google, in the global AI race.

China’s proposed standards will cover training for large language models (LLMs), which are the foundation of generative AI services like ChatGPT. Additionally, they will address safety, governance, industrial applications, software, computing systems, data centers, and the technical requirements and testing methodologies for semiconductors.

According to MIIT, these standards are expected to apply to at least 1,000 Chinese technology companies. The document also states that China will participate in creating at least 20 international AI standards, the report said.

MIIT’s draft policy identifies 12 critical technologies in the AI supply chain, including LLMs, natural language processing, computer vision, and machine learning, which involves systems performing complex tasks akin to human problem-solving. The draft policy also identifies four layers that comprise China’s AI industry chain: the foundation (including the computing power, algorithms, and data needed to train LLMs), the framework, the model, and applications.

Citing an industrial expert, the report indicated that the latest draft policy, unlike the usual command-and-control regulations, has adopted a pro-market, soft-law approach to guide and promote China’s AI industry. This stance, which is comparatively innovation-oriented and market-friendly, will not only enable the establishment and development of an AI ecosystem, but benefit other industries as well.

China’s tech giants, led by Huawei, has been aggressively advancing in the AI arena. Previously, Huawei claimed its second-generation AI chip “Ascend 910B” could compete with NVIDIA’s A100 and was working to replace NVIDIA, which holds over 90% of the market share in China. However, according to ChosunBiz, the chip, being manufactured by China’s leading semiconductor foundry, SMIC, has been in mass production for over half a year, yet the yield rate remains around 20%.

On the other hand, in response to US export bans, NVIDIA has commenced to sell H20, its AI chip tailored for the Chinese market earlier this year.

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• [News] Huawei Faces Production Challenges with 20% Yield Rate for AI Chip
• [News] NVIDIA Reportedly Facing Price Cut Pressure of H20 Chip in China Amid Competition with Huawei

According to a report from Economic Daily News, TSMC’s advanced packaging platform SoIC is said to have secured another heavyweight customer, with Apple expected to adopt the technology in 2025. If confirmed, Apple will join AMD as a major client expanding its use of TSMC’s SoIC .

TSMC has categorized advanced packaging under its 3D Fabric system integration platform, which comprises three main parts: the SoIC series for 3D silicon stacking technology, and the CoWoS and InFo families for back-end advanced packaging.

Reportedly, it is said that the CoWoS family has been facing capacity constraints recently. To address this, TSMC is not only expanding its own production but also collaborating with testing service providers to increase output.

On the other hand, TSMC’s SoIC platform, which is part of front-end packaging, has fewer bottlenecks and began small-scale production in 2022. TSMC has long-term plans to expand SoIC capacity by more than 20 times by 2026 to meet growing customer demand.

In recent years, NVIDIA and AMD have been aggressively targeting the AI market, setting high growth targets for 2024. Both companies have sought collaboration with TSMC and several Taiwanese supply chain partners. The key advantage is Taiwan’s comprehensive supply chain, which can accelerate innovation. As TSMC’s advanced packaging capacity ramps up, industry analysts are optimistic that this will facilitate the smooth procurement and delivery of critical components.

In the highly anticipated SoIC area, AMD’s MI300 series is a recent story of deepened collaboration with TSMC. According to information from AMD and TSMC’s technology forum, the MI300 series not only uses TSMC’s 5nm process but also integrates multiple technologies from TSMC’s 3DFabric platform. This includes stacking the 5nm GPU and CPU on a base chip using SoIC-X technology and further integrating them into CoWoS packaging.

Beyond AMD’s adoption, the same report has cited rumors that Apple might adopt this technology in 2025.

Although TSMC consistently refrains from commenting on individual client details, industry speculation has long suggested that Apple intends to incorporate related technology into the next-generation M-series chips, and possibly even the A-series processors. This could significantly increase transistor density, driving the next wave of innovation in the mobile device and AI PC markets.

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• [News] TSMC Reportedly Secures 4 Major Clients for SoIC, Including Apple, NVIDIA and Broadcom
• [News] TSMC’s SoIC Demand Heats Up, Reports Suggest Significant Capacity Expansion

(Photo credit: TSMC)

As semiconductor manufacturing enters the Angstrom Era, there have been significant adjustments in architecture and circuit design. To free up more surface area on chips, moving power delivery to the backside has become a mainstream consensus, making the Backside Power Delivery Network (BSPDN) the premier solution in advanced manufacturing.

According to a report from Commercial Times, regarding BSPDN, leading companies such as TSMC, Intel, and imec (Belgian Microelectronics Research Center) have proposed different approaches focusing on wafer thinning, atomic layer deposition (ALD) inspection, and wafer regeneration solutions, with mass production starting from 2026, benefiting supply chains.

Among them, TSMC’s Super Power Rail is considered direct and effective, albeit complex and expensive to implement. To reflect its value, TSMC has adjusted its pricing strategy. According to the report, the foundry leader has successfully raised prices for advanced processes, with further increases slated for January 1 next year, particularly targeting the 3/5-nanometer AI product lines with adjustments ranging from 5% to 10%.

Industry sources cited by the same report point out that there are several technological breakthroughs in backside power delivery. One critical aspect involves polishing the wafer backside to a thickness close enough for transistor contact. However, this process significantly compromises the wafer’s rigidity. Therefore, after front-side polishing, it’s essential to bond a carrier wafer to support the backside manufacturing process.

Additionally, technologies like nano Through-Silicon Vias (nTSV) require more equipment for ensuring uniform copper metal deposition within nano-scale holes.

Therefore, leading companies have proposed different approaches focusing on wafer thinning, atomic layer deposition (ALD) inspection, and wafer regeneration solutions. This development is benefiting related supply chain entities such as Kinik Company, Skytech, and Phoenix Silicon International Corporation.

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• [News] How Costly is the High-NA EUV? TSMC Reportedly Shocked, Considering Not Using the Equipment in its A16 Node
• [News] EUV as a Strategic Asset in the Most Advanced Processes: Progress in Intel/TSMC/Samsung’s Adoptions

(Photo credit: TSMC)