According to a report from Japanese news outlet Kyodo News, TSMC’s Fab in Kikuyo, Kumamoto Prefecture, Japan (Kumamoto Fab 1) is expected to start mass production in Q4 this year. The planned second Fab (Kumamoto Fab 2) will also be located in Kikuyo. Reportedly, TSMC’s Kumamoto Fab 2 has already begun land preparation, the construction of the fab is set to commence as scheduled in the second half of the year, with the goal of commencing operations by 2027.

The report indicates that Kumamoto Fab 2 is situated to the east of Kumamoto Fab 1, which held its opening ceremony in February. Per Japan’s Ministry of Economy, Trade, and Industry, the land area for Kumamoto Fab 2 is approximately 321,000 square meters, about 1.5 times larger than Kumamoto Fab 1 (an increase of around 50%). The investment for this project is estimated at around JPY 2.2 trillion yen, with the Japanese government providing subsidies of up to JPY 732 billion.

Kumamoto Fab 1 is expected to begin mass production in Q4 of this year, utilizing 28/22nm and 16/12nm process technologies with a monthly capacity of 55,000 wafers.

On February 6th, TSMC announced the construction of Kumamoto Fab 2 in Kumamoto Prefecture. Combined, the total investment for both Fabs is expected to exceed USD 20 billion. Construction of Kumamoto Fab 2 is scheduled to start at the end of 2024, with the goal of beginning operations by the end of 2027, focusing on 6/7nm technology. The combined monthly capacity of Kumamoto Fab 1 and Fab 2 is estimated to exceed 100,000 wafers.

Kumamoto’s newly appointed governor, Takashi Kimura, who took office in April, stated in an report from Bloomberg on May 11th that he would spare no effort to persuade TSMC to establish a third fab in the region. Kimura believed that during the preparations for TSMC’s first fab in Kumamoto, the region already possesses better-quality road and water infrastructure and an education system that better supports international school students, which could be advantageous.

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(Photo credit: TSMC)

According to TrendForce’s latest memory spot price trend report, the spot price of DRAM remains weak, as Samsung’s reallocation of its D1A process to the manufacturing of HBM products did little help. As for NAND flash, overall transactions are also sitting on the enervated end due to weakening market demand. Details are as follows:

DRAM Spot Price:

A fire-related incident occurred at Micron’s fab in Taichung on June 20th, but no actual losses (in bit terms) have been reported. In response to this event, module houses did temporarily suspend quoting, but they soon resumed trading activities. Overall, the event has had no positive effect on the spot price trend, which remains relatively weak. Similar to last week, spot trading has been fairly tepid, and prices of DDR4 products have fallen more significantly compared to DDR5 products. With Samsung reallocating its D1A process to the manufacturing of HBM products, spot prices of DDR5 products have actually experienced sporadic hikes for a while. Mainstream die DDR4 1Gx8 2666 MT/s saw a price increase of 1.36% this week (US$1.835 to US$1.860).

NAND Flash Spot Price:

Module houses have started adopting even more aggressive pricing strategies to effectively control their inventory, though overall transactions are sitting on the enervated end due to weakening market demand. TrendForce believes that inventory pressure would continue to bring down spot prices, which dropped to US$3.302 for 512Gb TLC wafers this week at a 0.21% reduction.

According to a report from the Economic Daily News, amid the escalating US-China tech war, Chinese President Xi Jinping emphasized the need to enhance the sense of urgency and intensify efforts in technological innovation. Particularly in six key areas, including semiconductors, industrial machinery, and advanced materials, China aims to ensure the independence, security, and control of crucial industrial and supply chains, striving to become a technological powerhouse by 2035.

During the speech Xi delivered while presenting China’s top sci-tech award on June 24th, he stated that building China into a technological powerhouse has been a persistent goal of the Chinese nation since modern times. As per the same report, by 2035, China aims to possess world-leading technological strength and innovation capability, which will support a significant leap in economic strength, national defense strength, and comprehensive national power.

Xi also called for China to focus on six key areas, including addressing bottlenecks in integrated circuits (semiconductors), industrial machinery, basic software, advanced materials, and scientific research instruments by intensifying technological research and development efforts. The goal is to ensure that critical industrial and supply chains are self-sufficient, secure, and controllable, providing technological support for these areas.

Furthermore, he urged targeting the strategic high ground of future technological and industrial development, accelerating innovation in next-generation information technology, artificial intelligence (AI), quantum technology, biotechnology, new energy, and new materials. The aim is to foster the growth of emerging and future industries.

Regarding the current international situation, Xi mentioned that the technological revolution and major power rivalries are intertwined, making high-tech fields the forefront and main battleground of international competition. He also acknowledged that China’s capability for original innovation remains relatively weak, with some critical core technologies dependent on others and a shortage of top scientific talent.

Earlier this month, Huawei also reportedly acknowledged that China’s semiconductor development may have plateaued. Per a report from Business Korea, Zhang Ping’an, the Chief Executive Officer of Huawei Cloud Services, noted that manufacturing 3.5 nm semiconductors necessitates EUV lithography machines, which Huawei is reportedly working on independently. However, overcoming U.S. and Dutch patents to internalize this technology is considered highly challenging.

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• [News] US to Lobby Netherlands and Japan to Contain China’s Chip Development, Focusing on HBM
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(Photo credit: iStock)

Driven by memory giants ramping up high-bandwidth memory (HBM) production, according to a report from Korean media outlet TheElec, ASMPT, a back-end equipment maker, has supplied a demo thermal compression (TC) bonder for Micron’s HBM production.

TC bonders play a pivotal role in HBM production by employing thermal compression to bond and stack chips on processed wafers, thereby significantly influencing HBM yield.

ASMPT is reportedly collaborating with the US memory giant to co-develop a TC bonder for use in HBM4 production. Notably, ASMPT has supplied TC bonders to SK Hynix as well and plans to deliver more units later in the year.

Micron is also procuring TC bonders from Shinkawa and Hanmi Semiconductor for the production of HBM3e. However, as per the same report citing sources, Shinkawa has its handful in supplying the bonders to its largest customer, so Micron added Hanmi Semiconductor as a secondary supplier.

In addition to Micron, Samsung Electronics and SK Hynix have developed distinct supply chains for TC bonders. Samsung sources its equipment from Japan’s Toray and Sinkawa, as well as its subsidiary SEMES. In contrast, SK Hynix relies on Singapore’s ASMPT, HANMI Semiconductor, and Hanhwa Precision Machinery.

According to industry sources cited by The Chosun Daily, TC bonder orders driven by memory giants have been strong, as Samsung Electronics’ subsidiary SEMES has delivered nearly 100 TC bonders over the past year. Meanwhile, SK Hynix has inked a approximately $107.98 million contract with HANMI Semiconductor, which commands a 65% share of the TC bonder market.

Regarding the latest developments in HBM, TrendForce indicates that HBM3e will become the market mainstream this year, with shipments concentrated in the second half of the year. Currently, SK hynix remains the primary supplier, along with Micron, both utilizing 1beta nm processes and already shipping to NVIDIA.

According to TrendForce predictions, the annual growth rate of HBM demand will approach 200% in 2024 and is expected to double in 2025.

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• [News] Rising HBM Production by Samsung and SK Hynix Energizes Korea’s TC Bonder Industry
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(Photo credit: Micron)

TSMC’s advanced CoWoS packaging capacity is in severe shortage, and just as the new plant in the Chiayi Park of Southern Taiwan Science Park began construction for expansion, according to a report from Economic Daily News citing sources, it has stated that TSMC intends to build another advanced packaging plant in Pingtung, which is located in southern Taiwan, and is currently in the site selection phase.

Regarding these rumors, TSMC has not yet responded. The relevant authorities, the Taiwanese National Science and Technology Council, stated that they have not heard of this and emphasized that any information about new plant constructions should be released by the company itself.

Currently, TSMC’s in-house packaging and testing capacities are located in Longtan, Hsinchu Science Park, Zhunan, Central Taiwan Science Park, and Southern Taiwan Science Park, with a new plant under construction in the Chiayi Park of Southern Taiwan Science Park. However, construction of one plant in the Chiayi Park was recently suspended due to the possible discovery of a historical site, prompting TSMC to initiate the construction of a second plant in the area.

If the advanced packaging plant in Pingtung is established, TSMC will have seven advanced packaging and testing sites in Taiwan, spanning across Taoyuan, Hsinchu, Miaoli, Taichung, Chiayi, Tainan, and Pingtung.

TSMC Chairman C.C.Wei previously mentioned that the demand for CoWoS capacity exceeds supply. Despite continuous expansion, TSMC still cannot meet all customer needs. Consequently, TSMC has increased outsourcing to professional packaging and testing subcontractors. TSMC is striving to expand its advanced CoWoS packaging capacity, with a target to more than double its in-house capacity this year and continue efforts next year to narrow the gap between supply and demand.

Industry sources cited in Commercial Time’s previous report have further indicated that by the end of next year, TSMC’s monthly CoWoS capacity will be increased to 60,000 wafers. With growing orders and a steep learning curve, the annual capacity is expected to surpass 600,000 wafers next year. As the semiconductor industry advances into the Angstrom Era, the gap in TSMC’s advanced packaging capacity will gradually widen.

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• [News] TSMC Halts Chia-Yi Plant Construction Due to Relic Found, Quickly Initiates Preparation for 2nd Plant
• [News] CoWoS Booming, TSMC Price Hikes Reportedly Imminent

(Photo credit: TSMC)