Due to the impact of international situations and uncontrollable factors, the global semiconductor supply chain is undergoing a shift. According to a report from WeChat account DRAMeXchange, the Southeast Asian region, with its advantages in labor and development conditions, has become the preferred location for major global companies. Countries such as Malaysia, India, and Singapore have been targeted by many manufacturers, who are rapidly setting up operations to secure a foothold.

On June 5, Taiwan-based contract chipmaker Vanguard International Semiconductor Corp. (VIS) announced to team up with Netherlands-based semiconductor supplier NXP Semiconductors N.V. to set up a joint venture, VisionPower Semiconductor Manufacturing Company (VSMC), and build a 12-inch fab in Singapore.

The fab will have an investment of approximately USD 7.8 billion. VIS will invest USD 2.4 billion and take a 60% stake, with NXP to invest USD 1.6 billion and a 40% share. The fab will be operated by VIS.

Besides, both parties have promised to allocate a total of USD 1.9 billion of long-term capacity security deposit and usage fees, with the remaining funds (Loans included) to be provided by third parties.

VSMC will run as an independent wafer manufacturing service provider, offering a certain proportion of its capacity to both partners. By 2029, the fab’s monthly 12-inch wafer capacity is expected to reach 55,000 pieces, which is projected to create around 1,500 jobs in Singapore. Following the successful mass production of the first fab, both sides will consider building a second one.

This fab will use 130nm to 40nm technologies to produce mixed-signal, power management, and analog products for markets including automotive, industrial, consumer electronics, and mobile terminals. Relevant technology licensing and transfers are expected to come from TSMC. VSMC will commence construction of the first fab in 2H24 , pending approval from relevant regulatory authorities, and it is expected to start mass production in 2027.

Currently, VIS has five 8-inch fabs, respectively located in Taiwan and Singapore. Three of them are based in Hsinchu (Taiwan) and one in Taoyuan (Taiwan). In 2023, the average monthly capacity was about 279,000 8-inch wafers.

On this collaboration with NXP, VIS Chairman Fang Leuh stated that both parties wish to own a 12-inch fab as they currently only have 8-inch fabs. More than half of the new fab’s capacity has already reserved upon long-term commitments from customers, including NXP. He also noted that setting up a fab in Singapore offers several advantages.

Since VIS is held by TSMC, industry experts believe that the establishment of the new VIS fab is driven in part by the need to meet the demands of TSMC’s mature process customers. Mature processes above 90nm account for a small single-digit percentage of TSMC’s revenue but retaining all customers is also necessary to match orders from various manufacturing capacities.

As such, VIS will take over TSMC’s customer orders. Influenced by multiple factors, the order transfer effect is expanding, and VIS has recently received new orders from several customers, like Qualcomm and MPS. That means order transfer effect in 2H24 has become evident.

It is worth noting that Singapore is being seen as a critical hub of the Asian semiconductor industry. It currently boasts a complete semiconductor industry chain, covering design, manufacturing, packaging, test, equipment, materials, and distribution, with more than 300 semiconductor-related companies already established.

According to another report from WeChat account DRAMeXchange, multitudes of semiconductor companies, including Texas Instruments, STMicroelectronics, Infineon, Micron, GlobalFoundries, TSMC, UMC, VIS, and ASE, have set up branches or expanded production in Singapore.

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• [News] TSMC Affiliate VIS and NXP to Invest USD 7.8 Billion for 12-Inch Fab in Singapore, Expected Mass Production by 2027
• Taiwanese Chipmakers Expand Overseas to Capitalize on Geopolitical Shifts and De-Sinicization Benefits, Says TrendForce

(Photo credit: VIS)

Last year, Qualcomm entered the PC market, sparking an AI PC frenzy in collaboration with Microsoft Copilot+. According to Qualcomm CEO Cristiano Amon, beyond mobile devices, PCs, and automotive applications, Qualcomm is now focusing on data centers. In the long term, these products will eventually adopt Qualcomm’s in-house developed Nuvia architecture.

Amon pointed out that as PCs enter a new cycle and AI engines bring new experiences, just as mobile phones require slim designs but must not overheat or become too bulky, Qualcomm has always been focused on technological innovation rather than just improving power consumption. While traditional PC leaders may emphasize TOPS (trillions of operations per second), energy and efficiency are also crucial.

Amon stressed the importance of maintaining battery life and integrating functionalities beyond CPU and GPU, which he believes will be key to defining leadership in the PC market. He also joked that if you use an X86 computer, it would run out of battery quickly, but with a new computer (AI PC) next year, it would last a long time without draining power.

Amon noted that Qualcomm’s Snapdragon X Elite and Snapdragon X Plus have been developed with superior NPU performance and battery life. Moreover, Snapdragon X Elite is just the first generation, which focuses more on performance supremacy, while the upcoming generations may put more emphasis on computational power, and integrating these into chip design.

Currently, more than 20 AI PCs equipped with Snapdragon X Elite and Snapdragon X Plus have been launched, including models from 7 OEMs, such Acer, Asus, Dell, HP, and others.

Amon believed that the market penetration rate will continue to increase next year. He sees AI PCs as a new opportunity, suggesting that it may take some time for them to be widely adopted when a new version of Windows for PC market emerges. However, considering the end of Windows 10 support, users can transition to new models with Copilot+, which he believes will be adopted much faster.

Amon pointed out that NPUs have already demonstrated their advantages in the PC and automotive chip industries, and these capabilities can be extended to data centers or other technologies.

He then highlighted data centers as a significant opportunity for transition to Arm architecture and expressed belief in increased opportunities for edge computing in the future. Amon also mentioned the adoption of Nuvia architecture in smartphones, data centers, and automotive industries. Additionally, he disclosed plans to launch mobile products featuring Microsoft processors at the October Snapdragon Annual Summit.

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• [News] Qualcomm CEO Reportedly Considers Collaboration with Samsung to Diversify Smartphone Chip Foundry Sources
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(Photo credit: Qualcomm)

The latest data released by the International Semiconductor Industry Association (SEMI) has shown that due to the sharp decline in the Taiwanese and North American markets, global semiconductor equipment billings contracted 2% year-over-year to US$26.4 billion in the first quarter of 2024.

According to SEMI’s press release, President and CEO Ajit Manocha noted that despite the slight dip in global semiconductor equipment billings, the industry remains strong and resilient. “Strategic investments and demand for advanced technology will catalyze the semiconductor equipment market’s return to growth,” he stated.

It is worth noting that the Chinese market sales in Q1 reached USD 12.52 billion, a 113% jump from the same period last year, maintaining its position as the world’s largest chip equipment market for the fourth consecutive quarter.

One the other hand, the South Korean market saw a 7% decline in sales to USD 5.2 billion, ranking as the second largest chip equipment market in the world for the third consecutive quarter, surpassing Taiwan, while Taiwan’s market sales plummeted by 66% to USD 2.34 billion, experiencing the largest decline among major markets.

Additionally, sales in the European market surged by 23% to USD1.89 billion, whereas sales in the US market plummeted by 33% to USD1.89 billion. The Japanese market saw a 4% decline in sales to USD 1.82 billion, and sales in other regions dropped by 28% to USD 760 million.

On the other hand, the World Semiconductor Trade Statistics (WSTS) has shown its optimism on the semiconductor industry by adjusting its spring 2024 forecast upwards on 4^th June, projecting a 16% growth in the global semiconductor market compared to the previous year, which reflects stronger performance in the last two quarters, particularly in computing end-markets. The updated market valuation for 2024 now stood at USD 611 billion.

According to WSTS, mainly two categories are anticipated to drive the growth for 2024 with double digit increase, logic (10.7% YoY) and memory (76.8% YoY). Conversely, other categories such as discrete, optoelectronics, sensors, and analog semiconductors are expected to experience single-digit declines.

Looking beyond 2024, an earlier projection from TrendForce suggests that foundry capacity, which makes significant contribution to chip equipment sales, tend to show similar change of pattern with SEMI’s data.

According to Trendfroce, as of 2024, per the overall foundry capacity, Taiwan is expected to hold approximately 44% of global market share, followed by China (28%), South Korea (12%), the US (6%), and Japan (2%). However, the overall semiconductor production capacities of Taiwan and South Korea are projected to decrease to 40% and 10%, respectively, by 2027.

China, where foundries focus more on expanding mature process capacities and are backed by government subsidies, is projected to perform relatively strong in the overall global market share, growing from 28% in 2024 to 31% in 2027.

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• [Insights] Trendforce: Foundry Capacity Market Share of Advanced Process to Decline in Taiwan, Korea until 2027, While US on the Rise

According to a report from TechNews, South Korean memory giant SK Hynix is participating in COMPUTEX 2024 for the first time, showcasing the latest HBM3e memory and MR-MUF technology (Mass Re-flow Molded Underfill), and revealing that hybrid bonding will play a crucial role in chip stacking.

MR-MUF technology attaches semiconductor chips to circuits, using EMC (liquid epoxy molding compound) to fill gaps between chips or between chips and bumps during stacking. Currently, MR-MUF technology enables tighter chip stacking, improving heat dissipation performance by 10%, energy efficiency by 10%, achieving a product capacity of 36GB, and allowing for the stacking of up to 12 layers.

In contrast, competitors like Samsung and Micron use TC-NCF technology (thermal compression with non-conductive film), which requires high temperatures and high pressure to solidify materials before melting them, followed by cleaning. This process involves more than 2-3 steps, whereas MR-MUF completes the process in one step without needing cleaning. As per SK Hynix, compared to NCF, MR-MUF has approximately twice the thermal conductivity, significantly impacting process speed and yield.

As the number of stacking layers increases, the HBM package thickness is limited to 775 micrometers (μm). Therefore, memory manufacturers must consider how to stack more layers within a certain height, which poses a significant challenge to current packaging technology. Hybrid bonding is likely to become one of the solutions.

The current technology uses micro bump materials to connect DRAM modules, but hybrid bonding can eliminate the need for micro bumps, significantly reducing chip thickness.

SK Hynix has revealed that in future chip stacking, bumps will be eliminated and special materials will be used to fill and connect the chips. This material, similar to a liquid or glue, will provide both heat dissipation and chip protection, resulting in a thinner overall chip stack.

SK Hynix plans to begin mass production of 16-layer HBM4 memory in 2026, using hybrid bonding to stack more DRAM layers. Kim Gwi-wook, head of SK Hynix’s advanced HBM technology team, noted that they are currently researching hybrid bonding and MR-MUF for HBM4, but yield rates are not yet high. If customers require products with more than 20 layers, due to thickness limitations, new processes might be necessary. However, at COMPUTEX, SK Hynix expressed optimism that hybrid bonding technology could potentially allow stacking of more than 20 layers without exceeding 775 micrometers.

Per a report from Korean media Maeil Business Newspaper, HBM4E is expected to be a 16-20 layer product, potentially debuting in 2028. SK Hynix plans to apply 10nm-class 1c DRAM in HBM4E for the first time, significantly increasing memory capacity.

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• [News] Reasons for Samsung’s HBM Chips Failing Nvidia Tests Revealed, Reportedly Due to Heat and Power Consumption Issues
• [News] HBM Boom May Lead to DRAM Shortages in the Second Half of the Year

(Photo credit: SK Hynix)

Samsung has been strengthening its alliance regarding the semiconductor packaging technology, attempting to narrow the technological gap with TSMC, according to the latest report by Business Korea.

Citing industry sources, Business Korea noted that Samsung is expected to expand its 2.5D and 3D MDI (Multi Die Integration) Alliance to include 30 partners this year, an increase of 10 within just one year.

The MDI Alliance, launched by Samsung Electronics in June, 2023, was established to address the rapid growth in the chiplet market for mobile and HPC applications, in which Samsung will collaborate with its partner companies as well as major players in memory, substrate packaging and testing.

According to Samsung’s press release, the MDI Alliance leads innovation in stacking technology by forming a packaging technology ecosystem for 2.5D and 3D Heterogeneous Integration. Together with partners across the ecosystem, Samsung will provide a one-stop turnkey service to better support customers’ technological innovation.

As demands from AI and data centers have been heated up, stacking and combining different chips are viewed as more cost-effective and efficient than further reducing the circuit size within a chip, which makes 2.5D and 3D IC packaging technology coveted by tech giants like NVIDIA and AMD.

Business Korea further stated that while Samsung does benefit from offering a ‘one-stop’ solution that integrates foundry, HBM, and packaging, successful collaboration is crucial to address the various software challenges that arise from chip integration. That is to say, to overcome this challenge, Samsung has formed a coalition with design firms, post-processing companies, and EDA (Electronic Design Automation) tool providers.

On the other hand, TSMC, the current market leader in 2.5D IC and 3D IC packaging, announced the new 3Dblox 2.0 open standard and its major achievements of its Open Innovation Platform (OIP) 3DFabric Alliance in September, 2023, while AMD confirmed its collaboration with TSMC on 3D IC packaging for the GPU giant’s MI300 AI accelerators, according to a press release by TSMC.

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• [News] Differences Between 3D-SIP and 3D-SIC: Why Are TSMC, Intel, and Samsung All Actively Involved?

(Photo credit: Samsung)