The 2024 Computex Taipei has kicked off, with NVIDIA CEO Jensen Huang delivering a speech on the industry’s prospects and future amidst the AI wave. According to a report from Commercial Times, during a media interview on the evening of June 3, Huang revealed plans for NVIDIA to establish an R&D center in Taiwan within the next five years.

Jensen Huang pointed out that NVIDIA already has a great AI research team. He confirmed the importance of Taiwanese partners, stating that TSMC is very important to NVIDIA’s operations, as well as expressing gratitude to partners such as Foxconn, Quanta, and ASUS for their support.

Huang further mentioned that within the next five years, NVIDIA will set up a large design center in Taiwan, indicating that the GPU giant is looking for a very spacious location and will hire at least 1,000 engineers.

When asked by the media about the speculation regarding his meeting with AMD CEO Lisa Su, Huang revealed that he did not attend her speech but acknowledged that AMD is a great company. He mentioned that he doesn’t expect to meet Su but didn’t rule it out the possiblity completely, adding that if it happens, he would welcome it.

Read more

• [News] A Recap of NVIDIA’s Four Major Application Areas of New Technology from Jensen Huang
• [News] AMD Unveils MI325, Claiming 30% Faster Computing Power than NVIDIA’s H200

(Photo credit: AMD)

The application period for the tax incentives under Taiwan’s Chip Act ended in late May. According to a report from the Economic Daily News, the Ministry of Economic Affairs announced on June 3rd that four semiconductor-related companies have applied, with the review process expected to be completed by mid to late July. Reportedly, it is said that major semiconductor companies, such as TSMC and MediaTek, have submitted their applications.

Under this act, eligible companies can benefit from certain tax deduction measures, including a 25% tax deduction for expenses on cutting-edge innovative R&D expenses and a 5% deduction on expenses of advanced process equipment, reportedly to be the most generous tax deduction measures ever in Taiwan.

The first round of applications from enterprises was accepted in February of this year, with the deadline on May 31st.

Regarding the eligibility criteria, according to the investment deduction measures announced by the Ministry of Economic Affairs, an eligibility company’s R&D expenses must reach NTD 6 billion, while its R&D intensity be at least 6%, and expenditures on equipment for advanced processes must reach NTD 10 billion.

The aforementioned criteria are not restricted by industry category. However, an effective tax rate of 12% for 2023 is required to qualify for the tax reductions under Article 10-2 of the Statute for Industrial Innovation.

Per the same report, it is understood that in 2023, there are nine listed companies meeting the two major thresholds, namely, reaching the NTD 6 billion threshold for R&D expenses and an R&D intensity of 6%, of which TSMC and MediaTek may potentially benefit from.

The Industrial Development Bureau stated that only four companies have applied for the tax benefits under the Taiwan Chip Act. They did not disclose the names of these companies, only mentioning that all applicants are semiconductor-related firms. It is widely anticipated that TSMC and MediaTek, the two most competitive companies in the country with the highest investment in R&D, are likely to benefit from the Taiwan Chip Act.

Read more

• [News] Taiwan’s Chip Act Takes Effect in February, TSMC to Benefit from Historic Tax Incentives

(Photo credit: TSMC)

On May 31, STMicroelectronics announced to build a new high-volume 200mm silicon carbide (SiC) facility in Catania, Italy, for power devices and modules as well as test and packaging.

According to a report from WeChat account DRAMeXchange, the new plant aims to commence production in 2026 and ramp to full capacity by 2033, with a full production capacity of up to 15,000 wafers per week. The total investment is expected to be around EUR 5 billion, with a support of around EUR 2 billion provided by the State of Italy in the framework of the EU Chips Act.

ST stated that Catania Silicon Carbide Campus will serve as the central hub of ST’ s global SiC ecosystem, integrating all steps in the production flow, including SiC substrate development, epitaxial growth processes, 200mm front-end wafer fabrication and module back-end assembly, as well as process R&D, product design, advanced R&D labs for dies, power systems and modules, and full packaging capabilities. This will achieve a first of a kind in Europe for the mass production of 200mm SiC wafers.

Currently, ST is producing its flagship high-volume SiC products on two 150mm wafer production lines in Catania, Italy, and Ang Mo Kio, Singapore. The third center is a joint venture between ST and San’an, which is now building a 200mm plant in Chongqing, China, dedicated to serving ST’s Chinese customers.

ST’s wafer production facilities are supported by automotive-qualified, high-volume assembly and test operations in Bouskoura (Morocco) and Shenzhen (China). SiC substrate R&D and industrialization is undertaken in Norrköping (Sweden) and Catania, where ST’s SiC substrates manufacturing facility is ramping up production and most of ST’s SiC product R&D and design staff are based.

SiC is a compound semiconductor material with inherent properties that offer superior performance and efficiency in power applications compared to silicon. Driven by market demands in new energy vehicles, photovoltaic storage applications, the usage volume of SiC power devices continues to rise.

As per TrendForce’s survey, the market size of global SiC Power Device was around USD 3.04 billion in 2023 and is expected to grow to USD 9.17 billion by 2028 at a CAGR of 25%.

Read more

• [News] A Price War in SiC Wafer Sector seems to Start
• [News] Continuous Breakthroughs in SiC Substrates, Global 8-Inch Fab to Reach 11

(Photo credit: STMicroelectronics )

At TSMC’s 2024 Technology Symposium in late May, Kevin Zhang, TSMC Senior Vice President of Business Development, has shared the company’s latest development on advanced packaging. This article recaps the highlights in the forum, featuring TSMC’s breakthroughs regarding advanced packaging.

Advanced Packaging

SoW (System-on-Wafer Integration Technology)

SoW adopts TSMC’s InFO and CoWoS packaging technologies to integrate logic dies and HBM memory on the wafer. By doing so, TSMC aims to enhance performance and speed not just at the chip level, but the system level as well.

Currently, TSMC’s system-on-wafer manufactured with InFO technology has entered mass production. Afterwards, the company plans to develop and launch SOW using CoWoS technology to integrate SoC or SoIC, HBM, and other components together.

TSMC eyes its System-on-Wafer manufactured with the CoWoS technology to enter mass production in 2027, while its target applications would include AI and HPC, expanding the computational power needed for data centers of the next generation.

3DFabric

TSMC’s 3DFabric technology family includes three major platforms: SoIC, CoWoS, and InFO, encompassing both 2D and 3D front-end and back-end interconnect technologies.

SoIC

The SoIC platform offers two stacking solutions: SoIC-P (Bumped) and SoIC-X (Bumpless). The first solution, SoIC-P, is a micro-bump stacking solution suitable for cost-effective applications such as mobile devices.

The other solution, SoIC-X, adopts Hybrid Bonding, which is ideal for HPC and AI demands. The advantage of this solution is that the pitch between contacts can be reduced to a few micrometers (µm), increasing the interconnect interface between two chips while achieving a new level of interconnect density.

TSMC’s current bond pitch density with Hybrid Bonding has been reduced to 6 micrometers, and it aims to further reduce it 2 to 3 micrometers. In the meantime, the company has been advancing micro-bump technology, currently at over 30 micrometers, with the future goal of reducing it to the teens.

TSMC revealed that customer demand for SoIC-X technology has been increasing, with 30 customer design tape-outs expected by the end of 2026.

CoWoS / InFO

The CoWoS advanced packaging family includes three members: CoWoS-S, CoWoS-L, and CoWoS-R. The three platforms can mainly be differentiated by their intermediate layer materials, which may also affect the cost. In other words, CoWoS-S utilizes silicon interposer, CoWoS-L uses LSI (Local Silicon Interconnect), while CoWoS-R uses RDL (Redistribution Layer) wiring to connect small chips.

Depending on product requirements, SoIC chips can be integrated with either CoWoS or InFO. AMD’s MI300A / MI300 X is the first product to adopt SoIC-X and CoWoS technology.

One of the most well-known product which adopts TSMC’s CoWoS-L technology would be NVIDIA’s Blackwell AI accelerator, which integrates two SoCs using 5nm with eight HBM into one module.

Moreover, TSMC’s CoWoS technology integrates advanced SoCs/SoICs with HBM to meet the requirements of AI chips. Its SoIC has entered mass production through the CoWoS-S platform. Going forward, TSMC plans to develop a SoIC chip with an eight-time mask size (using the A16 process) and a CoWoS solution with 12 HBM stacks. This updated version is expected to enter mass production in 2027.

(Photo credit: TSMC)

AMD Chairman and CEO Lisa Su unveiled the company’s latest AI chip, MI325X, at the opening of Computex Taipei on June 3. She emphasized that the MI325X boasts 30% faster computing speed compared to NVIDIA’s H200. According to a report from CNA, Su also announced that AMD plans to release a new generation of AI chips each respective year, hinting at a strong competitive stance against NVIDIA.

Lisa Su announced that the MI300 series is AMD’s fastest progressing product. The tech giant’s next-generation AI chip, MI325X, features HBM3e and is built on the CDNA 3 architecture.

According to Su, AMD MI325X outperforms NVIDIA’s H200 in performance and bandwidth, more than twice than that of NVIDIA’s H200. On the other hand, MI325X delivers 30% faster computing speed compared to the H200.

Furthermore, Su also announced that AMD will release MI350 in 2025, which will be manufactured with 3nm process, while MI400 is expected to follow, launched in 2026.

On June 3, Lisa Su stated that AMD will continue its collaboration with TSMC, advancing process technology to the 3nm and even 2nm nodes. Yet, Su did not directly address the previous market rumors suggesting that AMD might switch to Samsung’s 3nm technology.

Previously, as per a report on May 29th from The Korea Economic Daily, it has speculated that AMD is likely to become a customer of Samsung Electronics’ 3nm GAA process. Reportedly, during AMD CEO Lisa Su’s appearance at the 2024 ITF World, which was hosted by the Belgian microelectronics research center imec, Su revealed that AMD plans to use the 3nm GAA process for mass-producing next-generation chips.

Per the same report, Lisa Su stated that 3nm GAA transistors can enhance efficiency and performance, with improvements in packaging and interconnect technology. This will make AMD products more cost-effective and power-efficient. The report further addressed that, as Samsung is currently the only chip manufacturer with commercialized 3nm GAA process technology, Su’s comments were interpreted as indicating that AMD will officially collaborate with Samsung for 3nm production.

Read more

• [News] South Korean Media Suggests AMD Could Become Samsung’s 3nm GAA Process Customer
• [News] Samsung Reportedly Signs USD 3 Billion HBM3e Deal with AMD

(Photo credit: AMD)